A method and apparatus for performing de-skew control are provided, where the method is applied to an electronic device. The method includes: buffering a plurality of data sequences for performing symbol detection on a plurality of channels; according to a first symbol on a first channel, determining corresponding first expected symbols on other channels to determine a plurality of candidate expected symbol positions on the other channels, respectively; according to at least one other symbol on the first channel, within the candidate expected symbol positions on the other channels, eliminating any candidate expected symbol position that does not comply with a predetermined format to obtain a plurality of expected symbol positions on the other channels; and utilizing the expected symbol positions as correct positions of the corresponding first expected symbols on the other channels to control respective data of the data sequences to be synchronously transmitted.

A method and system is provided for allowing signals across electrical domains. The method includes applying a clock signal (of at least 1 GHz) to an electronic element in a location having first electrical properties. Data is output from the first electronic element; and received at a second electronic element located in a location having second electrical properties. The first and second electrical properties are different by either voltage and clock frequency.

A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.

A communication system for interfacing a transmitting circuit with a receiving circuit includes a transmission interface for receiving data from the transmitting circuit and transmitting the data received over at least one data line in response to a transmission clock signal. The communication system also includes a reception interface configured for receiving the data in response to a reception clock signal and transmitting the data received to the receiving circuit. In particular, the system is configured for generating a plurality of clock signals that have the same frequency but are phase-shifted with respect to one another. In addition, during a calibration phase, the system is configured for selecting one of the clock signals for the transmission clock signal or reception clock signal via selecting at least one of the clock signals for transmission of test signals via the transmission interface and verifying whether the test signals received via the reception interface are correct. The system is further configured to use, during normal operation, the clock signal selected during the calibration phase for transmission of data.

An exemplary apparatus for converting fluctuations in periodicity of an input signal into proportional fluctuations in the amplitude of an output signal includes: an input line for accepting an input signal; a delay element with an input coupled to the input line and an output; a detector having a first input coupled to the input line, a second input coupled to the output of the delay element, and an output; an integrator having an input coupled to the output of the detector and an output; and an output line coupled to the output of the integrator. The delay element introduces a time delay which is greater than zero and less than twice the nominal oscillation period of the input signal. The detector performs a differencing operation. The integrator has a time constant of integration that is smaller than twice the delay applied by the delay element.

Systems, methods, and apparatus for regenerating a data signal and a clock signal are provided. One of the apparatuses include clock regeneration loop circuitry configured to receive an input data signal transmitted without a reference clock signal, and to generate an output reference clock signal having an adjustable clock frequency that substantially matches a data rate of the input data signal; data detection loop circuitry configured to generate a phase offset control signal for adjusting a phase of a clock signal that samples the input data signal, and to generate, based on the phase offset control signal, a sampled input data signal; and an elastic buffer configured to generate, based on the output reference clock signal and the sampled input data signal, an output data signal that substantially aligns with the output reference clock signal, and enable the different adaptation dynamic of the loops.

A method and a circuitry to perform clock and data recovery, CDR is provided. The method includes the steps of obtaining an analogue communication signal characterized by a symbol frequency F.sub.symbol; and performing an analogue-to-digital conversion of the analogue communication signal according to a sampling rate F.sub.sample targeting F.sub.symbol*(M/L) thereby obtaining a digital signal. The method includes up-sampling the digital signal by L; filtering the up-sampled digital signal with filter coefficients of a finite impulse response, FIR, filter to perform a fractionally-spaced equalisation; and down-sampling the filtered digital signal by M resulting in a recovered digital signal. Intermediate filter coefficients are obtained for the FIR filter and a phase error is determined based on the recovered digital signal. The intermediate filter coefficients are interpolated based on the phase error to compensate for the phase error, resulting in interpolated filter coefficients; and the filter coefficients of the FIR filter are updated with the interpolated filter coefficients.

Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.

Techniques for enabling a rapid clock frequency transition are described. An example of a computing device includes a Central Processing Unit (CPU) that includes a core and noncore components. The computing device also includes a dual mode FIFO that processes data transactions between the core and noncore components. The computing device also includes a frequency control unit that can instruct the core to transition to a new clock frequency. During the transition to the new clock frequency, the dual mode FIFO continues to process data transactions between the core and noncore components.

A source-synchronization interface circuit includes: a sender synchronous-to-asynchronous protocol converter that receives sender data and a sender clock and that has regenerative gain to resolve metastability during phase synchronization of the sender clock and a receiver clock; an asynchronous FIFO buffer with multiple stages that conveys phase information and data from the sender synchronous-to-asynchronous protocol converter to a receiver synchronous-to-asynchronous protocol converter; and a receiver synchronous-to-asynchronous protocol converter that receives the receiver clock and that has regenerative gain to resolve metastability during the phase synchronization. Moreover, the source-synchronization interface circuit includes control logic that initializes the source-synchronization interface circuit by operating the stages in the asynchronous FIFO buffer in a slow mode having a cycle time less than a data-transfer period for a predetermined number of clock cycles, and subsequently operating the stages in a normal mode having a cycle time that is less than that for the slow mode.