The present invention relates to a method for synchronising a node in a deterministic mesh network, in particular a network of sensors using a channel hopping (TSCH) transmission medium access mode. Each node measures the successive synchronisation offsets of its local clock in relation to those of neighbour nodes with which it enters into communication, the measurement being carried out by detecting a reception event of a packet transmitted by the neighbour node or an acknowledgement of a packet transmitted by said node to the neighbour node. The node estimates from these synchronisation offsets, a synchronisation offset for the timeslot and corrects its local clock by a fraction of the synchronisation offset thus estimated. Said fraction may be determined by means of multi-agent reinforcement learning (MARL), each agent being associated with a node of the network.

Data words are received in parallel in response to an edge of a master clock signal and selected for serial output in response to a select signal. For a detected temporal offset of the serially output data words, the generation of the select signal and the master clock signal are controlled to correct for the temporal offset by shifting timing of the edge of the master clock signal and adjusting a sequence of values for the select signal that are generated within one cycle of the master clock signal. For a backward temporal offset, at least one count value in the sequence of values is skipped and the edge of the master clock signal occurs earlier in time. For a forward temporal offset, at least one count value in the sequence of values is held and the edge of the master clock signal occurs later in time.

A plurality of synchronization FIFOs receive input data streams from corresponding transmitting agents. Data is written to the synchronization FIFOs based on write clock signals provided by the corresponding transmitting agents. An arbitration circuit reads data from the synchronization FIFOs based on an asynchronous local clock signal. A minimum number of entries (S.sub.MIN) of each synchronization FIFO is specified by a number of entries required to synchronize the stored data to the local clock signal. S.sub.MIN may further be specified by: a number of entries required to store data during a threshold time period that a throughput of the input data streams may exceed a read data throughput enabled by the local clock signal; a number of entries required to store the data during a flow control response time; and a number of entries read from the synchronization FIFO during the threshold time period and the flow control response time.

This application provides a drive and a data transmission method, to implement low-latency transmission. The drive includes a CDR circuit, an elastic buffer, a receiver circuit, and a transmitter circuit. The CDR circuit is configured to recover a receive clock from a received signal. The receiver circuit is configured to recover sent data from the received signal by using the receive clock. The elastic buffer is configured to move the sent data in by using the receive clock and move the data out by using the receive clock. The transmitter circuit is configured to send the sent data from the elastic buffer by using the receive clock.

A conversion pipeline includes a media input stage, a packetizer, a MAC engine and a PHY interface. The media input stage is configured to receive from a media source a sequence of media frames carrying media content. The packetizer is configured to convert the media frames into a sequence of Ethernet packets by generating headers and appending portions of media frames to corresponding generated headers, including appending a first portion of a first media frame to a first generated header before the first media frame is fully received. The MAC engine is configured to commence outputting a first Ethernet packet as an uninterrupted unit, the first Ethernet packet including the first header and payload bits corresponding to the first portion of the first media frame, before the first media frame is fully received. The PHY interface is configured to transmit the Ethernet packets over a network.

A plurality of synchronization FIFOs receive input data streams from corresponding transmitting agents. Data is written to the synchronization FIFOs based on write clock signals provided by the corresponding transmitting agents. An arbitration circuit reads data from the synchronization FIFOs based on an asynchronous local clock signal. A minimum number of entries (S.sub.MIN) of each synchronization FIFO is specified by a number of entries required to synchronize the stored data to the local clock signal. S.sub.MIN may further be specified by: a number of entries required to store data during a threshold time period that a throughput of the input data streams may exceed a read data throughput enabled by the local clock signal; a number of entries required to store the data during a flow control response time; and a number of entries read from the synchronization FIFO during the threshold time period and the flow control response time.

A media content converter, for converting media content into network packets, includes logic circuitry, a header generator and a multiplexer. The logic circuitry is configured to partition the media content into payloads for the network packets. The header generator configured to generate packet headers for the network packets, by populating with data a plurality of header fields according to a predefined header format. The multiplexer is configured to stream a sequence of the network packets for transmission over a communication network, by combining the generated packet headers from the header generator with the corresponding payloads from the logic circuitry.

A conversion pipeline includes a media input stage, a packetizer, a MAC engine and a PHY interface. The media input stage is configured to receive from a media source a sequence of media frames carrying media content. The packetizer is configured to convert the media frames into a sequence of Ethernet packets by generating headers and appending portions of media frames to corresponding generated headers, including appending a first portion of a first media frame to a first generated header before the first media frame is fully received. The MAC engine is configured to commence outputting a first Ethernet packet as an uninterrupted unit, the first Ethernet packet including the first header and payload bits corresponding to the first portion of the first media frame, before the first media frame is fully received. The PHY interface is configured to transmit the Ethernet packets over a network.

A radio communication repeater for operating in a Time Division Multiple Access radio communication system with a plurality of time slots to transmit packets. The repeater includes a transmitter to transmit a plurality of the packets in a transmit time slot assigned to that repeater and a receiver to receive a plurality of the packets from all other time slots of the TDMA radio communication system other than the transmit time slot assigned to that repeater. The repeater also includes a controller to process the received packets from all other time slots of the TDMA radio communication system other than the transmit time slot assigned to that repeater and, if the received packets have different recipient identifiers, to forward the received packets for transmission by the transmitter in the transmit time slot assigned to that repeater as a frame comprising a plurality of packets having different recipient identifiers.

Systems and methods for asynchronous data communication are disclosed. The system includes one or more peripheral devices, a processing device, and one or more communication channels. Each peripheral device includes a peripheral clock and a quantizer. The processing device is remotely located from each peripheral device and includes a processor clock that is asynchronous with at least one peripheral clock, an analog continuous time filter, and an analog-to-digital converter. The analog continuous time filter filters one or more quantized signals generated by the one or more peripheral devices to generate one or more filtered signals. The analog continuous time filter has a filter bandwidth corresponding to a signal bandwidth of one or more analog time varying signals represented by the one or more quantized signals. The analog-to-digital converter generates one or more converted signals by sampling the one or more filtered signals based on a processor clock signal.