Data words are received in parallel in response to an edge of a master clock signal and selected for serial output in response to a select signal. For a detected temporal offset of the serially output data words, the generation of the select signal and the master clock signal are controlled to correct for the temporal offset by shifting timing of the edge of the master clock signal and adjusting a sequence of values for the select signal that are generated within one cycle of the master clock signal. For a backward temporal offset, at least one count value in the sequence of values is skipped and the edge of the master clock signal occurs earlier in time. For a forward temporal offset, at least one count value in the sequence of values is held and the edge of the master clock signal occurs later in time.

A method in a clocked integrated circuit receiving an input clock signal having a clock frequency and a command signal for accessing a memory element in the clocked integrated circuit. The method detects the input clock signal having a clock frequency above or below a frequency threshold. The method generates a clock detect output signal having a first logical state in response to the clock frequency being below the frequency threshold and generates the clock detect output signal having a second logical state in response to the clock frequency being above the frequency threshold. The method delays the command signal by a first timing latency to generate a timing adjusted control signal where the first timing latency is one or more clock periods of the input clock signal. Finally, the method adjusts the first timing latency in response to the clock detect output signal.

The present invention relates to a multi-channel IM-DD optical transceiver comprising at least one transmitter and a receiver, and a method for equalizing input samples at an adjusted sampling phase using a quality parameter linearly proportional to a BER. The data transmission and reception use a single master channel and slave channels, which have a baud rate equal to or lower than the baud rate of the master channel. A reliable and identical clocking of all the channels is obtained through either the receiver clock of the master channel when they are received from a single transmitter or a reference clock whose frequency is higher than the highest clock frequency amongst all the channels when they are received from a combination of transmitters. An enhanced timing recovery circuit is also provided to select optimized finite impulse response filters, calculate filter coefficients and generate the receiver clock of the master channel.

A method for reading data from sensors is disclosed comprising: determining a sequence of measured data over time by means of a sensor, wherein the sequence of measured data over time is generated by step-by-step changes in the measured data at input times, which are determined by an input frequency fa and have a time interval of a period 1/fa of the input frequency; reading output data from the sensor at read times, which are determined by a read frequency fs and have a time interval of a period 1/fs of the read frequency, where the read frequency fs is smaller than the input frequency fa; determining, by means of a low-pass filter of the sensor, the ratio N between the input frequency fa and the read frequency fs from the sequence over time of the numbers of input times lying between two adjacent read times.

An FIR filter convolutes sampled data obtained by sampling a reception signal with tap coefficients. A phase difference detector detects a phase difference between a synchronization timing of a signal waveform estimated from an output signal of the FIR filter and a sampling timing of the output signal. A tap coefficient adjuster adjusts the tap coefficients so as to reduce the phase difference detected by the phase difference detector and causes the sampling timing of the output signal of the FIR filter to track the synchronization timing.

Solution for reducing timing uncertainty is provided. The solution means for receiving data in a first clock domain; means for selecting in the first clock domain a data unit to be a frame starting point and transmitting the information on the selection to a frame counter in a second clock domain; means for performing to the data in a coding/decoding unit coding or decoding, the coding/decoding unit several clock domains; means for obtaining at the output of the coding/decoding unit the position of the selected frame starting point; and means for determining timing of the correct frame starting point of the coded/decoded data utilizing the obtained position of the selected frame starting point and the information in the frame counter.

A wafer-level package includes a first die and a second die that are wafer-level packaged. The first die has a first clock source. The second die has a second clock source. The first clock source generates a clock shared by the first die and the second die. The second clock source, however, does not generate a clock used by any of the first die and the second die.

A method and system is provided for allowing signals across electrical domains. The method includes applying a clock signal (of at least 1 GHz) to an electronic element in a location having first electrical properties. Data is output from the first electronic element; and received at a second electronic element located in a location having second electrical properties. The first and second electrical properties are different by either voltage and clock frequency.

A method in a clocked integrated circuit receiving an input clock signal having a clock frequency and a command signal for accessing a memory element in the clocked integrated circuit. The method detects the input clock signal having a clock frequency above or below a frequency threshold. The method generates a clock detect output signal having a first logical state in response to the clock frequency being below the frequency threshold and generates the clock detect output signal having a second logical state in response to the clock frequency being above the frequency threshold. The method delays the command signal by a first timing latency to generate a timing adjusted control signal where the first timing latency is one or more clock periods of the input clock signal. Finally, the method adjusts the first timing latency in response to the clock detect output signal.

The invention relates to a method for transmitting data between a first unit which accumulates data that has been generated with a first frequency and a second unit which requests the accumulated data with a second frequency. The method has the steps of requesting a first total increment and a first value, which represents a time increment belonging to the first total increment, from the first unit, said first total increment being the data content of the accumulated data block provided at the request time in the first unit; generating a second total increment from the first total increment using the first value, the second total increment being the data content of a data block adapted to a nominal time increment of the second frequency; and transmitting the second total increment to the second unit.