A wafer-level package has a first die and a second die. The first die has a first clock source arranged to generate a first clock, a first sub-system arranged to generate transmit data, and an output circuit arranged to output the transmit data according to the first clock. The second die has a second sub-system, a second clock source arranged to generate a second clock, and an input circuit having an asynchronous first-in first-out (FIFO) buffer. The input circuit buffers the transmit data transferred from the output circuit in the asynchronous FIFO buffer according to the first clock, and outputs the buffered transmit data in the asynchronous FIFO buffer to the second sub-system according to the second clock.

The invention relates to methods for the conversion of data, which comprises at least the following steps. A number of asynchronously incoming data packets (P0, P1 . . . . P4) is received, wherein the data packets (DP) comprise input data (ED) with a first sample rate. The input data (ED) are assigned to positions in a filter buffer (22) based on the first sample rate. The input data (ED) are combined in the filter buffer (22) based on their respective position to form output data (SKD) with a defined second sample rate (SR2) in in course of a low-pass filtering (23). In the process the input data advance in the filter buffer (22) on a position-by-position and data-driven basis. The invention further relates to a conversion device (20) and a system (30) for the transmission of data as well as to the use of a filter buffer (22) in a conversion device (20) for the conversion of sample rates (SR1, SR2).

A data transfer circuit according to the invention includes a memory configured to write data in accordance with a write pointer in synchronization with a first clock, and read out the data in accordance with a readout pointer in synchronization with a second clock, a clock generation circuit configured to generate the second clock by multiplying a reference clock by a rational number N, a frequency error estimation circuit configured to estimate a frequency error between the first clock and the second clock based on a change amount of a pointer difference between the write pointer and the readout pointer, and an adjustment circuit configured to output, as an adjustment multiple N, a value obtained by dividing the estimated frequency error by a frequency of the reference clock. The clock generation circuit generates the second clock by multiplying the reference clock by a rational number (N+N).

Interface devices and systems that include interface devices are disclosed. In some implementations, a device includes a transceiver configured to transmit and receive data, a lane margining controller in communication with the transceiver and configured to control the transceiver to transmit, through a margin command, to an external device, a request for requesting a state of an elastic buffer of the external device, and control the transceiver to receive the state of the elastic buffer of from the external device, and a port setting controller adjust a clock frequency range of a spread spectrum clocking scheme based on the state of the elastic buffer.

A parallel transfer rate converter inputs first parallel data with number of samples being S1 pieces in synchronism with a first clock, and outputs second parallel data with number of samples being S2=S1(m/p) pieces (p is an integer equal to or larger than 1) in synchronism with a second clock having a frequency which is p/m times of a frequency of the first clock. A convolution operation device inputs the second parallel data in synchronism with the second clock, generates third parallel data with number of samples being S3=S2(n/m) pieces (S3 is an integer equal to or larger than 1) by executing a convolution operation with a coefficient indicating a transmission characteristic to the second parallel data, and outputs the third parallel data in synchronism with the second clock.

A method in a clocked integrated circuit receiving an input clock signal having a clock frequency and a command signal for accessing a memory element in the clocked integrated circuit. The method detects the input clock signal having a clock frequency above or below a frequency threshold. The method generates a clock detect output signal having a first logical state in response to the clock frequency being below the frequency threshold and generates the clock detect output signal having a second logical state in response to the clock frequency being above the frequency threshold. The method delays the command signal by a first timing latency to generate a timing adjusted control signal where the first timing latency is one or more clock periods of the input clock signal. Finally, the method adjusts the first timing latency in response to the clock detect output signal.

In one embodiment, an apparatus includes a clock channel to receive and distribute a clock signal to a plurality of data channels. At least some of the data channels may include: a first sampler to sample data; a second sampler to sample the data; and a deskew calibration circuit to receive first sampled data from the first sampler and second sampled data from the second sampler and generate a local calibration signal for use in the corresponding data channel. The apparatus may further include a global deskew calibration circuit to receive the clock signal from the clock channel, receive the first sampled data and the second sampled data from the plurality of data channels, and generate a global calibration signal for provision to the plurality of data channels. Other embodiments are described and claimed.

A method, algorithm, architecture, circuit and/or system that compensates for frequency difference in oversampled CDRs. The oversampled CDR uses a programmable divider whose division ratio is changed, for one or more cycles, from its usual division ratio, when accumulated phase movement in either direction exceeds a threshold. Accordingly, the elasticity buffer in oversampled CDRs can be made much smaller or entirely eliminated, resulting in less area, and reduced or eliminated dependence of max allowed burst size on ppm difference. The threshold can be kept programmable, and more than half unit interval, to provide robustness towards high frequency jitter.

A method and system is provided for allowing signals across electrical domains. The method includes applying a clock signal (of at least 1 GHz) to an electronic element in a location having first electrical properties. Data is output from the first electronic element; and received at a second electronic element located in a location having second electrical properties. The first and second electrical properties are different by either voltage and clock frequency.

Examples for performing static timing analysis on clocked circuits are described. An example static timing analysis computing device includes a logic device, and a storage device holding instructions executable by the logic device, the instructions including instructions executable to receive an input representative of one or more delays within a signal path in a cross-domain circuit, the cross-domain circuit configured to transfer data between a first domain having a first clock and a second domain having a second clock asynchronous with the first clock, receive an input representative of a static timing analysis constraint to be met by a signal traveling the signal path in the cross-domain circuit, apply the constraint in a static timing analysis of the signal path in the cross-domain circuit, and output a result based upon applying the static timing analysis constraint.