A coherent optical receiver includes equalizer circuitry having a plurality of taps, the equalizer circuitry being configured to receive an input signal and compensate for polarization mode dispersion affecting the input signal to generate a compensated input signal. The coherent optical receiver further includes error evaluation circuitry configured to calculate a determinant of a frequency-domain (FD) coefficient-based matrix using a plurality of tap signals from among the plurality of taps, adjust an error of convergence of the compensated input signal to generate an adjusted input signal, and iteratively adjust the determinant of the FD coefficient-based matrix based on the adjusted input signal to minimize the error of convergence.

Decision feedback equalization (DFE) tap systems and related apparatuses and methods are disclosed. An apparatus includes output nodes to provide output signals, a complementary metal-oxide-semiconductor (CMOS) DFE tap electrically connected to the output nodes, and a current integrating summer electrically connected to the output nodes. The current integrating summer is to reset the output nodes to a common mode voltage potential.

A test and measurement instrument has one or more input ports to connect the instrument to a device under test (DUT), one or more processors configured to execute code to cause the one or more processors to: receive an equalized waveform and an un-equalized waveform through the input port from the DUT, without any knowledge of a digital pattern that corresponds to the waveforms and without extracting the digital pattern from the waveforms, align the un-equalized waveform and the equalized waveform in time to produce an aligned un-equalized waveform and an aligned equalized waveform, and use the aligned equalized waveform and the aligned un-equalized waveform to determine equalizer tap values.

A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, the equalized input signal to generate multiple samples of a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

A method and structure for tap centering in a coherent optical receiver device. The center of gravity (CG) of the filter coefficients can be used to evaluate a proper convergence of a time-domain adaptive equalizer. However, the computation of CG in a dual-polarization optical coherent receiver is difficult when a frequency domain (FD) adaptive equalizer is adopted. In this case, the implementation of several inverse fast-Fourier transform (IFFT) stages is required to back time domain impulse response. Here, examples of the present invention estimate CG directly from the FD equalizer taps and compensate for an error of convergence based off of the estimated CG. This estimation method and associated device architecture is able to achieve an excellent tradeoff between accuracy and complexity.

Embodiments of this application disclose example phase detection methods, phase detection circuits, and clock recovery apparatuses. One example method includes receiving a first signal and deciding a (2M−1) level of the first signal to obtain a decision result, where the first signal is a (2M−1)-level signal, and M is a positive integer. A response amplitude parameter of a transmission channel can then be obtained. Clock phase information in the first signal can then be extracted based on the first signal, the decision result, and the response amplitude parameter. Output clock phase information can then be determined based on at least three decision results and at least three pieces of clock phase information in at least three symbol periods.

According to an aspect of an embodiment, a method may include assigning an activation window by an optical line terminal during a portion of an upstream transmitting window in a passive optical network (PON). The method may include performing a first modification to a first upstream transmission. The method may include performing a second modification to a second upstream transmission. The method may include receiving the first upstream transmission from a first optical network unit (ONU) during the activation window, the first ONU synchronized in the PON. The method may include receiving a second upstream transmission from a second ONU during the activation window, the second ONU requesting activation in the PON.

A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.

A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, to generate multiple samples for a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

A timing recovery apparatus for signal reception in a data transmission system comprises an equalizer to equalize a received signal and a phase detector connected after the timing recovery equalizer that generates a clock tone from absolute values of the received signal after equalization.