Patent classifications
H04L7/0058
REDUCED COMPLEXITY CONSTRAINED FREQUENCY-DOMAIN BLOCK LMS ADAPTIVE EQUALIZATION FOR COHERENT OPTICAL RECEIVERS
A method and structure for equalization in coherent optical receivers, Block-based LMS (BLMS) algorithm is one of the many efficient adaptive equalization algorithms used to (i) increase convergence speed and (ii) reduce implementation complexity. Since the computation of the equalizer output and the gradient of the error are obtained using a linear convolution, BLMS can be efficiently implemented in the frequency domain with the constrained frequency-domain BLMS (FBLMS) adaptive algorithm. The present invention introduces a novel reduced complexity constrained FBLMS algorithm. This new approach replaces the two discrete Fourier transform (DFT) stages required to evaluate the DFT of the gradient error, by a simple frequency domain filtering. Implementation complexity can be drastically reduced in comparison to the standard constrained FBLMS. Furthermore, the new approach achieves better performance than that obtained with the unconstrained FBLMS in ultra-high speed coherent optical receivers.
Receiver with Clock Recovery Circuit and Adaptive Sample and Equalizer Timing
A receiver is equipped with an adaptive phase-offset controller and associated timing-calibration circuitry that together shift the timing for a data sampler and a digital equalizer. The sample and equalizer timing is shifted to a position with less residual inter-symbol interference (ISI) energy relative to the current symbol. The shifted position may be calculated using a measure of signal quality, such as a receiver bit-error rate or a comparison of filter-tap values, to optimize the timing of data recovery.
Selectable-tap equalizer
A signaling circuit having a selectable-tap equalizer. The signaling circuit includes a buffer, a select circuit and an equalizing circuit. The buffer is used to store a plurality of data values that correspond to data signals transmitted on a signaling path during a first time interval. The select circuit is coupled to the buffer to select a subset of data values from the plurality of data values according to a select value. The equalizing circuit is coupled to receive the subset of data values from the select circuit and is adapted to adjust, according to the subset of data values, a signal level that corresponds to a data signal transmitted on the signaling path during a second time interval.
Channel diagnostics based on equalizer coefficients
A receiver applies a calibration method to compensate for skew between input channels. The receiver skew is estimated by observing the coefficients of an adaptive equalizer which adjusts the coefficients based on time-varying properties of the multi-channel input signal. The receiver skew is compensated by programming the phase of the sampling clocks for the different channels. Furthermore, during real-time operation of the receiver, channel diagnostics is performed to automatically estimate differential group delay and/or other channel characteristics based on the equalizer coefficients using a frequency averaging or polarization averaging approach. Framer information can furthermore be utilized to estimate differential group delay that is an integer multiple of the symbol rate. Additionally, a DSP reset may be performed when substantial signal degradation is detected based on the channel diagnostics information.
Symbol-rate phase detector for multi-PAM receiver
A multi-PAM equalizer receives an input signal distorted by inter-symbol interference (ISI) and expressing a series of symbols each representing one of four pulse amplitudes to convey two binary bits of data per symbol. High-order circuitry resolves the most-significant bit (MSB) of each two-bit symbol, whereas low-order circuitry 115 resolves the immediate least-significant bit (LSB). The MSB is used without the LSB for timing recovery and to calculate tap values for both MSB and LSB evaluation.
Voltage correction computations for memory decision feedback equalizers
A device includes a first terminal configured to receive a reference voltage, a second terminal configured to receive a weighted tap value, a local generator circuit configured to create a group of unsigned voltage correction values based on the reference voltage and the weighted tap value, and a sign configuring circuit configured to receive the group of unsigned voltage correction values from the local generator circuit and assign a polarity to each respective unsigned voltage correction value of the group of unsigned voltage correction values, creating correction signals from the group of unsigned voltage correction values. The device also includes an output configured to transmit the correction signals to a first input of a processing circuit, wherein the processing circuit is configured to use the correction signals to offset inter-symbol interference from a data stream on a distorted bit based at least on a control signal.
FORWARD AND BACKWARD PROPAGATION METHODS AND STRUCTURES FOR COHERENT OPTICAL RECEIVER
A method and structure for signal propagation in a coherent optical receiver device. Asynchronous equalization helps to reduce complexity and power dissipation, and also improves the robustness of timing recovery. However, conventional devices using inverse interpolation filters ignore adaptation algorithms. The present invention provides for forward propagation and backward propagation. In the forward case, the filter input signal is forward propagated through a filter to the adaptation engine, while, in the backward case, the error signal is backward propagated through a filter to the asynchronous domain. Using such forward and backward propagation schemes reduces implementation complexity while providing optical device performance.
Reduced complexity constrained frequency-domain block LMS adaptive equalization for coherent optical receivers
A method and structure for equalization in coherent optical receivers. Block-based LMS (BLMS) algorithm is one of the many efficient adaptive equalization algorithms used to (i) increase convergence speed and (ii) reduce implementation complexity. Since the computation of the equalizer output and the gradient of the error are obtained using a linear convolution, BLMS can be efficiently implemented in the frequency domain with the constrained frequency-domain BLMS (FBLMS) adaptive algorithm. The present invention introduces a novel reduced complexity constrained FBLMS algorithm. This new approach replaces the two discrete Fourier transform (DFT) stages required to evaluate the DFT of the gradient error, by a simple frequency domain filtering. Implementation complexity can be drastically reduced in comparison to the standard constrained FBLMS. Furthermore, the new approach achieves better performance than that obtained with the unconstrained FBLMS in ultra-high speed coherent optical receivers.
TAP CENTERER METHOD AND STRUCTURE FOR COHERENT OPTICAL RECEIVER
A method and structure for tap centering in a coherent optical receiver device. The center of gravity (CG) of the filter coefficients can be used to evaluate a proper convergence of a time-domain adaptive equalizer. However, the computation of CG in a dual-polarization optical coherent receiver is difficult when a frequency domain (FD) adaptive equalizer is adopted. In this case, the implementation of several inverse fast-Fourier transform (IFFT) stages is required to back time domain impulse response. Here, examples of the present invention estimate CG directly from the FD equalizer taps and compensate for an error of convergence based off of the estimated CG. This estimation method and associated device architecture is able to achieve an excellent tradeoff between accuracy and complexity.
CHARGE PUMP CIRCUITS FOR CLOCK AND DATA RECOVERY
The present invention is directed to electrical circuits. More specifically, embodiments of the present invention provide a charge pump, which can be utilized as a part of a clock data recovery device. Early and late signals are used as differential switching voltage signals in the charge pump. The first switch and a second switch are used for controlling the direction of the current flowing into the loop filter. Input differential voltages to the switches are being generated with an opamp negative feedback loop. The output voltage of the first switch and the second switch is used in conjunction with a resistor to generate a charge pump current. There are other embodiments as well.