A data receiver circuit includes a summer circuit configured to receive an input signal that encodes multiple data symbols, and combine the input signal with a feedback signal to generate an equalized input signal, which is used to generate a clock signal. The data receiver circuit also includes multiple data slicer circuits that sample, using the clock signal and multiple voltage offsets, to generate multiple samples for a particular data symbol. A precursor compensation circuit included in the data receiver circuit may generate an output value for the particular data symbol using the multiple samples. The data receiver circuit also includes a post cursor compensation circuit that generates the feedback signal using at least one of the multiple samples and a value of a previously received sample.

The present invention is directed to data communication. More specifically, embodiments of the present invention provide a transceiver that processes an incoming data stream and generates a recovered clock signal based on the incoming data stream. The transceiver includes a voltage gain amplifier that also performs equalization and provides a driving signal to track and hold circuits that hold the incoming data stream, which is stored by shift and holder buffer circuits. Analog to digital conversion is then performed on the buffer data by a plurality of ADC circuits. Various DSP functions are then performed over the converted data. The converted data are then encoded and transmitted in a PAM format. There are other embodiments as well.

Receivers, controller units for receivers and related methods are provided. One receiver includes an adjustable sample provider providing samples of an input signal using an adjustable sample timing and a feedback path providing a feedback signal to the adjustable sample provider based on a timing error. The feedback path includes a loop filter providing sample timing information to the adjustable sample provider and a replacement value provider providing a replacement sample timing information replacing the sample timing information when an input signal does not fulfil a predetermined requirement for a feedback-based sample timing adaptation. The replacement value provider provides the replacement sample timing information considering a timing error information over a longer time period when compared to a time period considered by the loop filter for a provision of the sample timing information.

There are provided examples of receivers, controller units and related methods, wherein one receiver includes: an adjustable sample provider configured to provide samples of an input signal using an adjustable sample timing; a feedback path configured to provide a feedback signal to the adjustable sample provider on the basis of a timing error, wherein the feedback path includes a loop filter configured to provide sample timing information to the adjustable sample provider; and a replacement value provider configured to provide a replacement sample timing information replacing the sample timing information provided by the feedback path when an input signal does not fulfil a predetermined requirement for a feedback-based sample timing adaptation, wherein the replacement value provider is configured to provide the replacement sample timing information considering a timing error information, or a quantity derived from the timing error information, over a longer time period when compared to a time period considered by the loop filter for a provision of the sample timing information.

Embodiments of this application disclose an error correction method and apparatus. The method includes: obtaining an output signal and an amplitude value of a feed forward equalizer FFE, where the amplitude value is a channel response amplitude value corresponding to an equivalent channel of the FFE; performing level decision on the output signal based on the amplitude value to obtain a first decision signal, where the first decision signal includes (2M1) decision symbols, and M is an integer not less than 2; performing (1/(1+D)) decoding on the first decision signal to obtain a first decoded signal, and determining the first decoded signal as a second decision signal, where the second decision signal includes (M1) decision symbols; if an absolute value of the second decision signal is greater than (M1), determining that a burst error occurs in the second decision signal; and correcting the burst error.

Embodiments of this application disclose a phase detection method, a phase detection circuit, and a clock recovery apparatus. The method includes: receiving a first signal, and deciding a (2M1) level of the first signal to obtain a decision result, where the first signal is a (2M1)-level signal, and M is a positive integer: obtaining a response amplitude parameter of a transmission channel; extracting clock phase information in the first signal based on the first signal, the decision result, and the response amplitude parameter; and determining output clock phase information based on at least three decision results and at least three pieces of clock phase information in at least three symbol periods. According to the foregoing method, a stable phase detection gain can be achieved when a clock phase is tuned to a pulse response edge

Embodiments include systems, devices, and methods for a combination CPHY/DPHY/eDP display transmission PHY. A CDE can include a MIPI display serial interface (DSI) circuitry configured to receive 8 bit data compliant with a DSI protocol and output a differential pair signal to a PISO circuit. The same data path is configured for incoming eDP data, which can be routed to circuitry configured to receive 10 bit data compliant with an eDP protocol and output a differential pair signal to a PISO circuit. The system can include a CPHY circuitry that includes a mapper circuit to map a 16 bit input to a 21 bit output, mapper circuit having three 7 bit outputs, and CPHY logic to output a trio. The MUX coupled to an output of the PISO is configured to output one of the eDP or the DSI or the CPHY data to an display driver.

The present disclosure provides a signal receiving apparatus having anti-RFI mechanism that includes an ADC circuit, an equalization circuit and a clock recovery circuit. The ADC circuit performs conversion of an input analog signal according to an internal clock signal, to generate an input digital signal. The equalization circuit equalizes the input digital signal such that the clock recovery circuit adjusts a phase of the internal clock signal and extracts a frequency by performing statistics on phase deviation amount information in a unit of a time window. The clock recovery circuit discards a corresponding phase deviation amount when a signal interference parameter of one of a sub time window is larger than a threshold value to update the phase deviation amount information, and generates an adjusting signal to adjust a frequency of the internal clock signal accordingly.

A Decision Feedback Equalizer (DFE) for filtering N symbols includes multiple processing blocks and selection logic. Each of the processing blocks includes a respective number N<N of lookahead modules. The processing blocks are arranged in groups of L processing blocks, and each processing block in a group receives (i) N symbols selected for the group from among the N symbols, and (ii) a predefined speculative value of a DFE output, and produces, based on the N symbols and on the predefined speculative value, N respective lookahead values. N1 of the N lookahead values are used in a chained calculation that meets a timing constraint that is not met by the chained calculation performed on N lookahead values. The selection logic selects one of the L lookahead values in each group of the L processing blocks for each of the N symbols, and outputs N lookahead values in parallel.

The present invention relates to an adaptive synchronization device for demodulating a signal in linear modulation (x). The device functions from a sampled version of the signal (x). The device being characterized in that it comprises: at least one synchronization module (F) comprising: at least one first sub-module (F.sub.n) arranged to deliver a first output signal (y) from the input signal (x) received at a period (T) less than the value (I) with (B) the bandwidth of the input signal (x); this first sub-module (F.sub.n) is capable of compensating a transmission delay of the input signal (x) by estimation of the propagation delay () between a transmitter and a receiver of a transmission medium; this first sub-module adapts the rate at its output to one sample per symbol; at least one second sub-module (F.sub.u) arranged to deliver a corrective () to be applied to the current estimation of the delay (), from an error term (w) defining the decision error of the device and the influence of the processings downstream of the first sub-module (F); at least one correction module of transmission imperfections (H), disposed downstream of the synchronization module (F) and forming a correction chain of transmission imperfections of the first output signal (y) received by this module (H) at the rhythm T, and comprising: at least one first sub-module (H.sub.n) arranged to deliver a second output signal (z) at the rhythm (T) estimating a stream of emitted symbols (ai); at least one second sub-module (H.sub.p) configured to deliver the error term (w), by application of a correction to an error term (v) for estimation of symbols to consider the influence of the processings included in the first sub-module (H.sub.n). $\begin{array}{cc}\left(\frac{1}{B}\right)& \left(I\right)\end{array}$