A communication device includes an interleaving unit that determines an interleaving length of transmit data to be transmitted through free-space optical communication, and interleaves the transmit data based on the determined interleaving length, and a shaping unit that shapes the interleaved transmit data so as to make the interleaving length detectable on a receiving side of the free-space optical communication.

To detect an error in pulse width in a communication scheme that identifies a start position of a message or expresses a data value using a pulse width of a pulse included in the message, provided is a receiving apparatus including a receiving section that receives a message including a synchronization pulse having a predetermined pulse width and a first data pulse having a pulse width corresponding to a value of first data; and an error detecting section that detects an error in response to the number of non-synchronization pulses that are consecutive after the synchronization pulse being outside a predetermined number range.

A communication device includes an interleaving unit that determines an interleaving length of transmit data to be transmitted through free-space optical communication, and interleaves the transmit data based on the determined interleaving length, and a shaping unit that shapes the interleaved transmit data so as to make the interleaving length detectable on a receiving side of the free-space optical communication.

A method for improving timing between solid state devices, e.g., in non-volatile memory device is described and includes generating timing signals from the data stream so that the data stream is free from synchronization bits. The PWM data stream is converted from CML to CMOS level. An even decoder decodes the even data signal. An odd decoder decodes the odd signal. The decoders rely on the respective signal, even or odd, to increase past a slower rising signal based on both the odd and even signals to change from a default low state to a high state. The clock signal is derived from edges of the data itself.

Wireless communication devices are adapted to facilitate scalable synchronization channels in a wireless communications system. According to one example, a wireless communication device may identify a reference synchronization channel including a reference bandwidth and a reference numerology, where the reference numerology includes a reference subcarrier spacing and a reference cyclic prefix. The reference synchronization channel may be scaled according to a type of communication, resulting in a scaled synchronization channel including a scaled bandwidth and a scaled numerology compatible with the communication type. According to another example, a wireless communication device may determine a communication type employed by the device for wireless communications, and may search for a particular scaled synchronization channel based on the determined communication type. Other aspects, embodiments, and features are also included.

A method for improving timing between solid state devices, e.g., in non-volatile memory device is described and includes generating timing signals from the data stream so that the data stream is free from synchronization bits. The PWM data stream is converted from CML to CMOS level. An even decoder decodes the even data signal. An odd decoder decodes the odd signal. The decoders rely on the respective signal, even or odd, to increase past a slower rising signal based on both the odd and even signals to change from a default low state to a high state. The clock signal is derived from edges of the data itself.

A receive clock generated at a receiver coupled to a one-wire bus is synchronized in each clock cycle, permitting reception of a data frame of unlimited length without clock overrun or underrun. A base clock signal provided by an oscillator is passed by a clock gating circuit while the clock gating circuit is enabled. A counter counts positive and negative edges in an output of the clock gating circuit. The clock gating circuit is disabled when an output of the counter indicates a preconfigured maximum count value. An edge synchronization circuit that synchronizes edges in the base clock signal with edges in a data signal received over the one-wire bus ignores edges in the data signal while the counter output has a value that is less than the maximum count value, and resets the counter in response to an edge detected in the data signal received over the one-wire bus.

A receiver circuit receives a transmission signal using serial communication, the transmission signal including image data and a synchronization signal that has a pulse period fluctuated in a predetermined fluctuation range. A data reception processing unit extracts the image data and the synchronization signal from the received transmission signal, and writes each line of the image data into a line memory among line memories while selecting the line memory line by line in turn in accordance with the synchronization signal. A line data reading unit reads each line of the image data from a line memory among the line memories while selecting the line memory line by line in turn in accordance with the synchronization signal. If the pulse period of the synchronization signal is not in the predetermined fluctuation range, an error detecting unit discards the image data written into the line memory in this pulse period.

Ultra-Wideband (UWB) wireless technology transmits digital data as modulated coded impulses over a very wide frequency spectrum with very low power over a short distance. Accordingly, the inventors have established UWB devices which accommodate and adapt to inaccuracies, errors, or issues within the implemented electronics, hardware, firmware, and software. Beneficially, UWB receivers may accommodate offsets in absolute frequency between their frequency source and the transmitter, accommodate drift arising from phase locked loop and/or from relative clock frequency offsets of the remote transmitter and local receiver. UWB devices may also employ modulation coding schemes offering increased efficiency with respect to power, data bits per pulse transmitted, and enabled operation at higher output power whilst complying with regulatory emission requirements. Further, UWB devices may support a ranging function with range/accuracy not limited to the low frequency master clock employed within these devices enabling operation with ultra-low power consumption.

A serial data receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. During startup of a communication channel, phase information generated by the analog receiver circuit may be used to generate clock signals for the ADC-based receiver circuit. After a period of time, the ADC-based receiver circuit can generate its own phase information to be used in the generation of the clock signals.