A receive clock generated at a receiver coupled to a one-wire bus is synchronized in each clock cycle, permitting reception of a data frame of unlimited length without clock overrun or underrun. A base clock signal provided by an oscillator is passed by a clock gating circuit while the clock gating circuit is enabled. A counter counts positive and negative edges in an output of the clock gating circuit. The clock gating circuit is disabled when an output of the counter indicates a preconfigured maximum count value. An edge synchronization circuit that synchronizes edges in the base clock signal with edges in a data signal received over the one-wire bus ignores edges in the data signal while the counter output has a value that is less than the maximum count value, and resets the counter in response to an edge detected in the data signal received over the one-wire bus.

To detect an error in pulse width in a communication scheme that identifies a start position of a message or expresses a data value using a pulse width of a pulse included in the message, provided is a receiving apparatus including a receiving section that receives a message including a synchronization pulse having a predetermined pulse width and a first data pulse having a pulse width corresponding to a value of first data; and an error detecting section that detects an error in response to the number of non-synchronization pulses that are consecutive after the synchronization pulse being outside a predetermined number range.

Embodiments of a method and a device are disclosed. In an embodiment, a method for operating a wired communications device involves including a frame boundary bit sequence and a random data sequence as a preamble of a bit stream, encoding the bit stream into an encoded bit stream, and transmitting the encoded bit stream using the wired communications device.

A receiver circuit includes a transition density detector circuit that generates a transition density signal based on a comparison between a transition density of data words to a transition density threshold. The receiver circuit also includes a bit shift and pattern detector circuit that bit shifts one of the data words to generate bit shifted data in response to the transition density signal indicating that the transition density of the data words has reached the transition density threshold. The bit shift and pattern detector circuit counts a number of bits shifts performed on the bit shifted data to locate a synchronization character. The receiver circuit also includes a word alignment circuit that bit shifts the data words by the number of bits shifts to generate word aligned data.

A digital receiver for decoding input data having three states includes a first input coupled to a first data line, a second input coupled to a second data line, a third input coupled to a third data line, and a fourth input coupled to a fourth data line. A first decoder is coupled to a first output, wherein the first decoder is for outputting first data signals in response to the sign of input data on the first data line minus input data on the second line. A second decoder is coupled to a second output, wherein the second decoder is for outputting second data signals in response to the sign of input data on the third data line minus input data on the fourth data line.

A receiver circuit receives a transmission signal using serial communication, the transmission signal including image data and a synchronization signal that has a pulse period fluctuated in a predetermined fluctuation range. A data reception processing unit extracts the image data and the synchronization signal from the received transmission signal, and writes each line of the image data into a line memory among line memories while selecting the line memory line by line in turn in accordance with the synchronization signal. A line data reading unit reads each line of the image data from a line memory among the line memories while selecting the line memory line by line in turn in accordance with the synchronization signal. If the pulse period of the synchronization signal is not in the predetermined fluctuation range, an error detecting unit discards the image data written into the line memory in this pulse period.

Exemplary systems and methods can be provided for measuring a parametere.g., channel impulse response and/or power delay profileof a wideband, millimeter-wave (mmW) channel. The exemplary systems can include a receiver configured to receive a first signal from the channel, generate a second signal, and measure the parameter based on a comparison between the first and second signals; and a controller configured to determine first and second calibration of the system before and after measuring the parameter, and determine a correction for the parameter measurement based on the first and second calibrations. Exemplary methods can also be provided for calibrating a system for measuring the channel parameter. Such methods can be utilized for systems in which the TX and RX devices share a common frequency source and for systems in which the TX and RX devices have individual frequency sources that free-run during channel measurements.

Ultra-Wideband (UWB) wireless technology transmits digital data as modulated coded impulses over a very wide frequency spectrum with very low power over a short distance. Accordingly, the inventors have established UWB devices which accommodate and adapt to inaccuracies, errors, or issues within the implemented electronics, hardware, firmware, and software. Beneficially, UWB receivers may accommodate offsets in absolute frequency between their frequency source and the transmitter, accommodate drift arising from phase locked loop and/or from relative clock frequency offsets of the remote transmitter and local receiver. UWB devices may also employ modulation coding schemes offering increased efficiency with respect to power, data bits per pulse transmitted, and enabled operation at higher output power whilst complying with regulatory emission requirements. Further, UWB devices may support a ranging function with range/accuracy not limited to the low frequency master clock employed within these devices enabling operation with ultra-low power consumption.

A serial data receiver circuit included in a computer system may include both an analog and an ADC-based receiver circuit. A front-end circuit generates different equalized signals based on received signals that encode a serial data stream that includes multiple data symbols. During startup of a communication channel, phase information generated by the analog receiver circuit may be used to generate clock signals for the ADC-based receiver circuit. After a period of time, the ADC-based receiver circuit can generate its own phase information to be used in the generation of the clock signals.

A signal transmission and reception system includes a transmission device configured to transmit a transmission signal, a reception device configured to receive the transmission signal, in which the transmission device includes a Manchester coding circuit that generates an encoded signal in which transmission data is converted into a Manchester code as a switching edge, as at least a part of the transmission signal on the basis of a transmission clock, and the reception device includes a high-speed clock generation circuit, an edge detection circuit configured to detect an edge of the transmission signal, and a signal detection circuit configured to detect the edge detected in a period sandwiched between a first elapsed time at which a first period has elapsed from a start point and a second elapsed time at which a second period longer than the first period has elapsed from the start point as the switching edge.