A receiving device 20 includes a voltage controlled oscillator 22, a sampling unit 23, a control voltage generating unit 24, an error detecting unit 25, and a control voltage holding unit 26. The control voltage holding unit 26 holds a value of a control voltage Vc output from the control voltage generating unit 24. When the error detecting unit 25 detects an error of a digital signal, a control voltage held before error detection is provided to the voltage controlled oscillator 22.

A receiving device includes: a receiver that receives a signal including PPM symbols; a clock generator that generates a clock for sampling; an A/D converter that digital-converts the received signal; a reference position detector that detects a leading position of the PPM symbols based on data from the A/D converter; and a clock error detector that detects a clock error. The clock error detector includes: a pulse position detector that detects a pulse position in the PPM symbols based on data from the reference position detector and A/D converter; a position error calculator that calculates a deviation of the pulse position based on data from the reference position detector, A/D converter, and pulse position detector; and a clock error calculator that calculates the clock error based on data from the position error calculator. The receiving device varies a frequency of the clock based on data from the clock error calculator.

A digital receiver for decoding input data having three states includes a first input coupled to a first data line, a second input coupled to a second data line, a third input coupled to a third data line, and a fourth input coupled to a fourth data line. A first decoder is coupled to a first output, wherein the first decoder is for outputting first data signals in response to the sign of input data on the first data line minus input data on the second line. A second decoder is coupled to a second output, wherein the second decoder is for outputting second data signals in response to the sign of input data on the third data line minus input data on the fourth data line.

Wireless communication devices are adapted to facilitate scalable synchronization channels in a wireless communications system. According to one example, a wireless communication device may identify a reference synchronization channel including a reference bandwidth and a reference numerology, where the reference numerology includes a reference subcarrier spacing and a reference cyclic prefix. The reference synchronization channel may be scaled according to a type of communication, resulting in a scaled synchronization channel including a scaled bandwidth and a scaled numerology compatible with the communication type. According to another example, a wireless communication device may determine a communication type employed by the device for wireless communications, and may search for a particular scaled synchronization channel based on the determined communication type. Other aspects, embodiments, and features are also included.

Exemplary systems and methods can be provided for measuring a parametere.g., channel impulse response and/or power delay profileof a wideband, millimeter-wave (mmW) channel. The exemplary systems can include a receiver configured to receive a first signal from the channel, generate a second signal, and measure the parameter based on a comparison between the first and second signals; and a controller configured to determine first and second calibration of the system before and after measuring the parameter, and determine a correction for the parameter measurement based on the first and second calibrations. Exemplary methods can also be provided for calibrating a system for measuring the channel parameter. Such methods can be utilized for systems in which the TX and RX devices share a common frequency source and for systems in which the TX and RX devices have individual frequency sources that free-run during channel measurements.

A digital receiver for decoding input data having three states includes a first input coupled to a first data line, a second input coupled to a second data line, a third input coupled to a third data line, and a fourth input coupled to a fourth data line. A first decoder is coupled to a first output, wherein the first decoder is for outputting first data signals in response to the sign of input data on the first data line minus input data on the second line. A second decoder is coupled to a second output, wherein the second decoder is for outputting second data signals in response to the sign of input data on the third data line minus input data on the fourth data line.

A communication device includes an interleaving unit that determines an interleaving length of transmit data to be transmitted through free-space optical communication, and interleaves the transmit data based on the determined interleaving length, and a shaping unit that shapes the interleaved transmit data so as to make the interleaving length detectable on a receiving side of the free-space optical communication.

A digital receiver for decoding input data having three states includes a first input coupled to a first data line, a second input coupled to a second data line, a third input coupled to a third data line, and a fourth input coupled to a fourth data line. A first decoder is coupled to a first output, wherein the first decoder is for outputting first data signals in response to the sign of input data on the first data line minus input data on the second line. A second decoder is coupled to a second output, wherein the second decoder is for outputting second data signals in response to the sign of input data on the third data line minus input data on the fourth data line.

A method for performing multi-wire signaling decoding is provided. A raw symbol spread over a plurality of n wires is received via a plurality of differential receivers. The raw symbol is converted into a sequential number from a set of sequential numbers. Each sequential number is converted to a transition number. A plurality of transition numbers is converted into a sequence of data bits. A clock signal is then extracted from the reception of raw symbols.

System, methods and apparatus are described that facilitate transmission of data over a multi-wire data communications link, particularly between two devices within an electronic apparatus. A clock extracted from a first sequence of symbols transmitted on a first lane of a multi-lane interface is used to receive and decode the first sequence of symbols and to receive and decode data and/or symbols transmitted on a second lane of the multilane interface. The clock signal may be derived from transitions in the signaling state of N wires between consecutive pairs of symbols in the first sequence of symbols. The first lane may be encoded using N! encoding and the second lane may be a serial or N! link.