A method includes receiving an optical signal through an optical link and determining a receiving power for the optical link. The method further includes comparing the receiving power for the optical link to a first receiving power threshold and transitioning a clock and data recovery circuit form a normal mode to a holdover mode when the receiving power is less than the first receiving power threshold. The clock and data recovery circuit, when operating in the holdover mode, configured to hold a recovered clock to a known-good clock frequency. When the receiving power for the optical link is greater than a second receiving power threshold, the method initiates a transition of the clock and data recovery circuit from the holdover mode to the normal mode and reacquires synchronization between the recovered clock and a current rate of the incoming data stream using the known-good clock frequency.

Disclosed herein are systems and methods for clock sustain in a two-wire communication systems and applications thereof. In some embodiments, in a clock sustain state, slave nodes with processors and digital to analog converters (DACs) may be powered down efficiently in the event of lost bus communication. For example, when the bus loses communication and a reliable clock cannot be recovered by the slave node, the slave node may enter the sustain state and, if enabled, signals this event to a general purpose input/output (GPIO) pin. In the clock sustain state, the slave node phase lock loop (PLL) may continue to run for a predetermined number of SYNC periods, while attenuating the inter-integrated circuit transmit (I2S DTXn) data from its current value to 0. After the predetermined number of SYNC periods, the slave node may reset and reenter a power-up state.

Embodiments herein relate to optoelectronic transceivers with power management. An optoelectronic device may include a photodetector, a loss of signal (LOS) detector coupled with the photodetector, and a re-timer coupled with the LOS detector, wherein a component of the re-timer is to be disabled in response to a detection by the LOS detector that an optical signal has not been received for a predetermined time period. In some embodiments, the LOS detector is coupled with a driver disable input of the re-timer and a driver component of the re-timer is to be disabled. In some embodiments, a clock data recovery circuit, a transmit module re-timer and modulator, and/or a laser may be disabled. In various embodiments, components may be re-enabled in response to detection that an optical signal is being received and/or an electrical signal is received for optical transmission. Other embodiments may be described and/or claimed.

A high frequency signal is down-converted into an intermediate frequency signal, transmitted over a limited bandwidth medium from a master unit to a remote unit and up-converted back into its original high frequency at the remote unit. The up-conversion is aided by reconstruction of a reference signal embedded at the master unit as a carrier for a management signal which is transmitted to the remote unit through the same limited bandwidth medium together with the intermediate frequency signal. The reference signal is reconstructed using a phase locked loop which includes a charge pump and is kept stable during intervals between bits and messages by a charge pump shutter.

In one embodiment, an apparatus comprises: a receiver to receive training data from a transmitter; a clock and data recovery (CDR) circuit coupled to the receiver, the CDR circuit to recover a recovered clock signal from the training data; and a media access control (MAC) circuit coupled to the CDR circuit, wherein the MAC circuit is to send a clock switch indicator to the CDR circuit to cause the CDR circuit to halt tracking operation of the CDR circuit. Other embodiments are described and claimed.

A receiver samples an analog, multi-level, pulse-amplitude-modulated signal using a clock-and-data recovery circuit (CDR) that samples the signal against adaptively calibrated symbol-decision thresholds in time with a clock signal that is phased aligned with and locked to the signal. The CDR can erroneously align the clock signal to inter-symbol edges of the signal, a condition called “edge lock,” rather than on the symbols themselves. A transition-type detector senses the edge-lock condition and unlocks the CDR, which can then realign the clock signal, this time on the symbols rather than the inter-symbol edges. The receiver can also respond to the edge-lock condition by kick-starting a shift of symbol-decision threshold that helps the CDR settle more quickly on correct symbol-decision thresholds.

According to one embodiment, a semiconductor integrated circuit includes: a converter configured to convert an analog signal into a digital signal based on a clock signal; a comparator configured to determine first data having data of a first number of bits per symbol and second data having data of a second number of bits, less than the first number, per symbol based on the digital signal; a recovery circuit configured to recover the clock signal; and a control circuit configured to input the digital signal and the first data to the recovery circuit in a case where a condition is not satisfied, and to input the digital signal and the second data to the recovery circuit in a case where the condition is satisfied.

A receiver samples an analog, multi-level, pulse-amplitude-modulated signal using a clock-and-data recovery circuit (CDR) that samples the signal against adaptively calibrated symbol-decision thresholds in time with a clock signal that is phased aligned with and locked to the signal. The CDR can erroneously align the clock signal to inter-symbol edges of the signal, a condition called “edge lock,” rather than on the symbols themselves. A transition-type detector senses the edge-lock condition and unlocks the CDR, which can then realign the clock signal, this time on the symbols rather than the inter-symbol edges. The receiver can also respond to the edge-lock condition by kick-starting a shift of symbol-decision threshold that helps the CDR settle more quickly on correct symbol-decision thresholds.

A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect “OSI” model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

A status control method, applied to an optical network unit (ONU) or an optical network terminal (ONT) of a passive optical network (PON) includes: receiving a first downlink data frame, where the first downlink data frame includes data of N different rates and indication information, the indication information includes length information of data of each rate in the first downlink data frame, and N≥2; determining length information of first data in the data of the N different rates, where a rate of the first data is higher than a working rate of a clock and data recovery (CDR) module; and generating control information based on the length information of the first data, to control the CDR module to be in a specified state within a period of time corresponding to the length information of the first data.