There are provided examples of receivers, controller units and related methods, wherein one receiver includes: an adjustable sample provider configured to provide samples of an input signal using an adjustable sample timing; a feedback path configured to provide a feedback signal to the adjustable sample provider on the basis of a timing error, wherein the feedback path includes a loop filter configured to provide sample timing information to the adjustable sample provider; and a replacement value provider configured to provide a replacement sample timing information replacing the sample timing information provided by the feedback path when an input signal does not fulfil a predetermined requirement for a feedback-based sample timing adaptation, wherein the replacement value provider is configured to provide the replacement sample timing information considering a timing error information, or a quantity derived from the timing error information, over a longer time period when compared to a time period considered by the loop filter for a provision of the sample timing information.

A communication device of the disclosure includes a phase synchronizer, a first modulator, and a detector. The phase synchronizer generates a second signal on a basis of a first signal received from a communication partner. The first modulator is able to modulate the first signal on a basis of the second signal. The detector detects that synchronization between the first signal and the second signal is lost.

A smart phase switching method includes setting a first phase switching threshold, a convergence upper bound, and a convergence lower bound, sampling a received signal continuously for acquiring a phase offset accumulated value of the received signal during each period, updating the first phase switching threshold to generate a second phase switching upper bound threshold and a second phase switching lower bound threshold when a plurality of phase offset accumulated values of the received signal during a first predetermined time interval fall into a range from the convergence upper bound to the convergence lower bound, and sampling the received signal continuously for determining if a phase is switched to an opposite operating point according to a phase offset accumulated value of the received signal after the second phase switching upper bound threshold and the second phase switching lower bound threshold are generated.

Systems and methods are described to enable synchronized encoding of streaming audio or video content between multiple encoders, in a manner that provides for seamlessly interchangeable encodings. A first encoding begins encoding streaming content at a first point in time, and at a later point in time, a second encoder is configured to begin encoding the streaming content in a manner synchronized with the first encoder. The second encoder communicates via a synchronization protocol with the first encoder, and receives state information of the first encoder, such as a timecode of the streaming content at which the first encoder began encoding. The second encoder uses the received state information to determine a difference in encoding start times between the first and second encoder, and to adjust its timestamp values to match those of the first encoder. Thereafter, the first and second encoders can encode content in a synchronized manner.

A method for transmitting real-time messages in a computer network (100), in particular real-time computer network, wherein said network comprises two or more computing nodes (21, 22, 23, 24, 25, 26) and one or more star couplers (1, 2, 3, 4), wherein said nodes are interconnected via at least one star coupler, wherein each node is connected to at least one star coupler via at least one of the communication links (50), and wherein the nodes exchange messages (M1, M2) with one another and with the at least one star coupler, and wherein star couplers, which are synchronized to a global time base (C), transmit a first non-empty set (SSET) of real-time messages according to a synchronized communication paradigm, and/or wherein computing nodes, which are synchronized to the global time base, transmit said first non-empty set of real-time messages according to the synchronized communication paradigm, wherein a star coupler, which is not synchronized to a global time base, and/or a computing node, which is not synchronized to a global time base, transmits a second non-empty subset (CSET) of said first non-empty subset of real-time messages according to an unsynchronized communication paradigm and stops the transmission of said second non-empty subset of real-time messages according to the synchronized communication paradigm.

A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect OSI model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

A network device may comprise one or more circuits including a clock signal generator, an ADC, and a processor. The ADC may digitize a received signal across a range of frequencies that encompasses a first band of frequencies used for a first network and a second band of frequencies used for a second network. A sampling frequency of the ADC may be determined by a frequency of a clock signal output by the clock signal generator. The processor may determine whether the first network is active and whether the second network is active. The processor may configure the clock generator such that, when both of the first network and the second network are active, the clock signal is set to a first frequency, and when the first network is active and the second network is inactive, the clock signal is set to a second frequency.

Example embodiments relate to transceiver devices with real-time clocks. One embodiment includes a transceiver device. The transceiver device includes a real-time clock arranged for providing a clock signal. The transceiver device also includes a receiving section. The receiving section includes a main receiver arranged for receiving communication signals. The receiving section also includes a wake-up receiver. The wake-up receiver is arranged for receiving a calibration signal that includes clock timing information containing a time stamp. The wake-up receiver is also arranged for adjusting the real-time clock based on the clock timing information.

Apparatus(es) and method(s) for CDR are described. In a CDR circuit, there is a bang-bang phase detector (BBPD), a baud-rate phase detector (BRPD), a multiplexer, and a control circuit. The BBPD, configured to receive data and crossing samples, generates a first result indicating a first phase difference between data and crossing samples. The BRPD, configured to receive data and peak samples, generates a second result indicating a second phase difference between data and peak samples. The multiplexer is configured to select either such result as a phase-detect output for a mode of operation. A control circuit is configured to clear a metastable state: for receipt of the first detect result, check for dithering, determine a direction for phase adjustment responsive to detection of the dithering, and provide a phase adjustment in the direction; and for receipt of the second detect result, operate to use the second phase difference generated.

Signal conditioning circuitry includes logic circuitry, a low-pass filter, and comparator circuitry. The logic circuitry is configured to compare a data unit with a preceding data unit, from a sequence of data units, and provide a logic output signal. The low-pass filter is coupled to the logic circuitry, and the low-pass filter is configured to provide a data transition density measurement for the sequence of data units based on the logic output signal. The comparator circuitry is coupled to the low-pass filter, and the comparator circuitry is configured to compare the data transition density measurement to a threshold and, based on the comparison to the threshold, indicate a disruptive pattern in the sequence of data units.