A system includes a link having one or more lanes associated with transmitting data and one or more lanes associated with transmitting a clock signal. The system includes a device coupled with the link, the device to receive a signal via the one or more lanes associated with transmitting the clock signal and determine a number of pulses associated with the signal over a period. The device is further to determine the number of pulses associated with the signal fail to satisfy a predetermined condition relating to a specified number of pulses for the period and initiate a power-down sequence in response to determining the number of pulses that fail to satisfy the predetermined condition relating to the specified number of pulses for the period.

A reset sub-circuit can sample the reset signal based on a low-speed clock reference signal to generate a series of sampled reset signals. A phase relation between a first selected one of the series of sampled reset signals and the high-speed clock signal at the clock input of each sampler can be measured to generate reset trigger signals corresponding to each of a plurality of samplers. A second selected one of the series of sampled reset signals can be sampled based on the high-speed clock signal to generate a positive sampled reset signal and a negative sampled reset signal. The reset sub-circuit can select between the positive sampled reset signal and the negative sampled reset signal based on the reset trigger signals corresponding to each sampler to generate the synchronous reset signal.

A receiver including an equalizer disposed upstream of a decimator and capable of effectively preventing undesirable interaction between equalization adaptation and the overall timing recovery loop in cases of various data rates. The equalizer operates in a full operation rate even in the case of a lower-than-full data rate, e.g., half or quarter data rate. For input analog signal having 1/M of the full data rate (M>1), M or more Center of Filter (COF) values are determine. Each COF may be derived from a function of a respective set of tap weights and compared with a corresponding nominal COF to obtain a COF offset. The resultant COF offsets are used as indications of clock phase correction caused by equalization adaptation to adjust a set of selected tap weights. The taps selected for adjustment encompass at least M samples to correctly indicate the COF offset associate with one symbol.

A system on a chip (SOC) is configured to support multiple time domains within a time-sensitive networking (TSN) environment. TSN extends Ethernet networks to support a deterministic and high-availability communication on Layer 2 (data link layer of open system interconnect OSI model) for time coordinated capabilities such as industrial automation and control applications. Processors in a system may have an application time domain separate from the communication time domain. In addition, each type time domain may also have multiple potential time masters to drive synchronization for fault tolerance. The SoC supports multiple time domains driven by different time masters and graceful time master switching. Timing masters may be switched at run-time in case of a failure in the system. Software drives the SoC to establish communication paths through a sync router to facilitate communication between time providers and time consumers. Multiple time sources are supported.

A reset sub-circuit can sample the reset signal based on a low-speed clock reference signal to generate a series of sampled reset signals. A phase relation between a first selected one of the series of sampled reset signals and the high-speed clock signal at the clock input of each sampler can be measured to generate reset trigger signals corresponding to each of a plurality of samplers. A second selected one of the series of sampled reset signals can be sampled based on the high-speed clock signal to generate a positive sampled reset signal and a negative sampled reset signal. The reset sub-circuit can select between the positive sampled reset signal and the negative sampled reset signal based on the reset trigger signals corresponding to each sampler to generate the synchronous reset signal.

Example embodiments relate to transceiver devices with real-time clocks. One embodiment includes a transceiver device. The transceiver device includes a real-time clock arranged for providing a clock signal. The transceiver device also includes a receiving section. The receiving section includes a main receiver arranged for receiving communication signals. The receiving section also includes a wake-up receiver. The wake-up receiver is arranged for receiving a calibration signal that includes clock timing information containing a time stamp. The wake-up receiver is also arranged for adjusting the real-time clock based on the clock timing information.

Provided is a reception apparatus capable of shortening a time period until the original data and clock can be recovered from a digital signal after temporary superimposition of noise on the digital signal stops. A reception apparatus 20 includes a receiver unit 21, a voltage-controlled oscillator 22, a sampler unit 23, a control voltage generation unit 24, an error detection unit 25, a training control unit 26, and an equalizer control unit 27. The receiver unit 21 includes an equalizer unit 21A. When the error detection unit 25 detects an error of a digital signal, the reception apparatus 20 causes a phase/frequency comparison by the control voltage generation unit 24 to be stopped.

According to one embodiment, a base station apparatus (1) includes: a radio equipment control (2) that generates a baseband signal including data (D1); a microwave apparatus (4) that modulates the baseband signal to a microwave to transmit by radio; a microwave apparatus (5) that demodulates the received first microwave to the baseband signal, then extracts a clock (CLK1) from a cycle of the data (D1) included in the baseband signal, imports the baseband signal in synchronization with the clock (CLK1), and plays back the data (D1); and a radio equipment (3) that modulates the data (D1) played back by the microwave apparatus (5) to a high-frequency signal, and the microwave apparatus (5) outputs dummy data instead of the played back data when a frequency fluctuation amount of the clock (CLK1) exceeds a predetermined range.

An integrated circuit is operable in two modes, including a test mode in which a pattern of variation is injected into a receiver's sampling clock and used to simulate jitter. Adding frequency offset, jitter or both, to this clock can be equivalent to adding jitter of an equal magnitude but opposite sign in a transmitted test signal. In this way, a clock can be produced that simulates timing variations that can be encountered during mission function operation of the device under test, while test input data is applied by local pattern generators or other data sources that, under test conditions, do not, or need not, exhibit such variations. In detailed embodiments, these techniques can be separately employed in one or more clock and data recovery circuits (CDRs) of the integrated circuit; for example, a first local clock recovery circuit in a first receiver can be caused to produce a test clock which simulates a condition to be tested, and while a second receiver in the plurality of receivers that includes a second local clock recovery circuit is caused to use the test clock in place of the reference clock while receiving a test data sequence at its input.

Techniques and apparatus for detection of a signal at an I/O interface module are described. In one embodiment, for example, an apparatus to provide signal detection may include at least one receiver, at least one memory, and logic for a signal detection module, at least a portion of the logic comprised in hardware coupled to the at least one memory and the at least one receiver, the logic to access a plurality of pulse signals of a clock and data recovery (CDR) circuit, analyze at least one pulse characteristic of the plurality of pulse signals, and generate a signal determination to indicate a signal at the at least one receiver based on the at least one pulse characteristic. Other embodiments are described and claimed.