A PAM-4 receiver with jitter compensation clock and data recovery is provided. The receiver includes a first-order delay-locked loop (DLL) which employs a bang-bang phase detector (BBPD) and a voltage-controlled delay line (VCDL) circuit supporting 40 MHz jitter tracking bandwidth and static phase skew elimination. A second-order wideband phase-locked loop (WBPLL) using the ¼-rate reference clock provides multi-phase clock generation with low input-to-output latency. To suppress the consequent jitter transfer, a jitter compensation circuit (JCC) acquires the jitter transfer amplitude and frequency information by detecting the DLL loop filter voltage (VLF(s)) signal, and generates an inverted loop filter voltage signal, denoted as VLF.sub.INV(s). The VLF.sub.INV(S) modulates a group of complementary VCDLs (C-VCDLs) to attenuate the jitter transfer on both recovered clock and data. With the provided receiver, a jitter compensation ratio up to 60% can be supported from DC to 4 MHz, with a −3-dB corner frequency of 40 MHz.

A radio apparatus correlates signal data with stored synchronization data to determine correlation data. The signal data represents a received radio-frequency signal that encodes a data frame, which has a synchronization preamble with a plurality of instances of a predetermined synchronization sequence. The stored synchronization data represents the predetermined synchronization sequence. The radio apparatus identifies a set of peaks in the correlation data, and uses a timing criterion to identify a plurality of subsets of the set of peaks, such that time values of the peaks of each identified subset satisfy the timing criterion. The radio apparatus calculates a correlation score C.sub.j for each of the identified subsets from correlation values of the subset's peaks, and uses the correlation scores C.sub.j to select a subset from the plurality of subsets. Timing or frequency synchronization information for the radio apparatus is determined from the peaks of the selected subset.

A method for recovering the symbol time by a receiver to decode a sequence of symbols transmitted by a transmitter when the symbol time of the transmitter is biased with respect to the symbol time of the receiver. When a transition is detected between two consecutive symbols, an absolute error on the instant of the current symbol is measured and a statistical model of the bias is updated. A correction may then be applied to the instants of the subsequent symbols depending on the measured absolute error and/or a bias estimated from the statistical model. During periods in which there are no transitions between symbols, an absolute error cannot be measured, but it is still possible to apply a correction to the instants of the subsequent symbols depending on a relative error extrapolated from the statistical model.

A channel between quantum controller modules (e.g., pulse processors) is operable to communicate high speed data required for processing qubit states that may be distributed across a quantum computer. The latency of the communication channel is deterministic and controllable according to a system clock domain.

An example apparatus includes: a feed forward equalizer (FFE) with a FFE output, adder circuitry with a first adder input, a second adder input, and a first adder output, the first adder input coupled to the FFE output, a multiplexer (MUX) with a first MUX input, a second MUX input, and a MUX output, the first MUX input coupled to the first adder output, the second MUX input coupled to the FFE output, a decision feedback equalizer (DFE) with a DFE output coupled to the second adder input, and a timing error detector (TED) with a first TED input coupled to the MUX output.

A communication chip includes an input port, a gain circuit, a correction circuit having a phase-locked loop (PLL) circuit and a return terminal, a post-processing circuit, and a switching circuit. The gain circuit includes an input terminal and a quadrature modulation circuit that operates according to a reference clock. The gain circuit gains a signal from the input terminal according to a bias voltage and outputs a gained signal. The PLL circuit generates a correction signal through synchronization according to the reference clock. The post-processing circuit obtains an input signal strength according to a correction table and a signal from a receiving terminal of the post-processing circuit. The switching circuit couples the correction signal to the input terminal and the gained signal to the return terminal in test mode and couples the input port to the input terminal and the gained signal to the receiving terminal in an operating mode.

A method of frequency search and error correction of clock and data recovery circuit, comprising: initializing a frequency search algorithm parameter; processing a frequency error parameter UP/DN signals according to the set algorithm parameter and starting the frequency search, in which, the algorithm accordingly counts the UP/DN signals. When a phase error signal transition occurs, a transition parameter JUMP is accumulated by 1, and an accumulation parameter SUM is obtained and is further judged that whether a frequency search result is to be output. Number of repeating times of verification and threshold parameters are set, accordingly a reset DCRL value is obtained to verifies a frequency locking result and outputs the result. The present invention improves accuracy of UP/DN pulse counting, increases stability and reliability of the frequency locking, avoids a false locking in the frequency locking, and prevents an excessive locking time in the frequency locking, overcomes error judgment of the frequency search caused by a random jitter, and correctly completes the frequency search and locking, avoids failure of the CDR caused by an error frequency locking.

Methods and systems are described for generating a time-varying information signal at an output of a continuous time linear equalizer (CTLE), asynchronously sampling a data signal according to a sampling clock having a frequency less than a data rate of the data signal; generating corresponding pattern-verified samples for at least two data patterns, each of the at least two data patterns having a respective frequency content; determining corresponding frequency-specific voltage measurements associated with each of the at least two data patterns based on the corresponding pattern-verified samples of the at least two data patterns; and adjusting an equalization of the data signal based on a comparison of the corresponding frequency-specific voltage measurements.

The data recovery from sub-carriers gradients (DRSG) of a received OFDM signal affected by deterministic and random distortions introduced by a transmission link, contributes a method and a circuit for utilizing gradients characterizing shapes of OFDM sub-carriers comprised in such OFDM signal for recovering data symbols transmitted originally.

A radio receiver device determines whether a digital radio signal includes a predetermined cyclic preamble. An input portion samples the digital radio signal and generates a plurality of samples for storage in a buffer. A first autocorrelator correlates first and second subsets of the samples to generate a first correlation metric, the second subset having been stored in the buffer earlier than said first subset by an even integer multiple of half of the preamble period. A second autocorrelator correlates first and third subsets of the plurality of samples to generate a second correlation metric, the third subset having been stored in the buffer earlier than said first subset by an odd integer multiple of half of the preamble period. A processing portion calculates a difference between the correlation metrics and determines that the radio signal includes the predetermined cyclic preamble when the difference is greater than a threshold value.