Some embodiments include apparatus and methods having an input to receive an input signal, additional inputs to receive clock signals having different phases to sample the input signal, and a decision feedback equalizer (DFE) having DFE slices. The DFE slices include a number of data comparators to provide data information based on the sampling of the input signal, and a number of phase error comparators to provide phase error information associated with the sampling of the input signal. The number of phase error comparators of the DFE slices is not greater than the number of data comparators of the DFE slices.

The present disclosure relates to a data driving device and a method of driving the data driving device and, more particularly, to a data driving device and a method of driving the same in which a tuning of a set value of an internal circuit is automatically performed.

A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

Embodiments are related to systems and methods for data processing, and more particularly to systems and methods for clock recovery in a data receiver.

A master device communicates with a slave device through an asynchronous serial communications link. The master device includes a single pad configured to communicate a command frame including an address and a data frame including data with the slave device via a single wire; and a processing circuit configured to generate an oversampling clock signal from a clock signal, to perform a synchronization process for selecting one of a plurality of clock phases of the oversampling clock signal, and to perform a sampling process for sampling an each bit value included in the data frame transmitted from the slave device using a clock phase at the same position as the clock phase selected during the synchronization process.

Embodiments herein describe sub-picosecond accurate two-way clock synchronization by optically combining received optical pulses with optical pulses generated locally in a photonic chip before the optical signals are then detected by a photodetector to obtain an interference measurement. That is, the optical pulses can be combined to result in different interference measurements. Optically combining the pulses in the photonic chip avoids much of the jitter introduced by the electronics. Further, the sites can obtain multiple interference measurements which can be evaluated to accurately determine when the optical pulses arrive at the site with femtosecond accuracy.

A low-power, high-performance source-synchronous chip interface which provides rapid turn-on and facilitates high signaling rates between a transmitter and a receiver located on different chips is described in various embodiments. Some embodiments of the chip interface include, among others: a segmented “fast turn-on” bias circuit to reduce power supply ringing during the rapid power-on process; current mode logic clock buffers in a clock path of the chip interface to further reduce the effect of power supply ringing; a multiplying injection-locked oscillator (MILO) clock generator to generate higher frequency clock signals from a reference clock; a digitally controlled delay line which can be inserted in the clock path to mitigate deterministic jitter caused by the MILO clock generator; and circuits for periodically re-evaluating whether it is safe to retime transmit data signals in the reference clock domain directly with the faster clock signals.

A symbol boundary in a data packet having a guard interval preceding a preamble having a predetermined sequence of symbols is detected by receiving a signal representing a data packet; sampling the received signal at a sampling rate; estimating channel impulse responses from a set of samples in dependence on the predetermined sequence of symbols of the preamble; determining an energy value for each of a plurality of windows of channel impulse responses, each of the windows corresponding to W number of consecutive samples, the energy value for each of the windows being indicative of the total energy associated with the channel impulse responses of that window; determining which of the windows has the greatest energy value; and identifying the earliest sample of the consecutive W samples in said determined greatest energy window, the earliest sample being indicative of a symbol boundary for the preamble.

The Data Recovery with Inverse Transformation (DRIT) comprises methods and systems for reversing transmission channel transfer function in order to achieve a direct recovery of original data from a received signal distorted by a transmission link.

A signal processing method executed by a transmission device, the signal processing method includes receiving a plurality of frame signals; extracting a plurality of synchronization signals each for performing frame synchronization and separating data of each of the plurality of frame signals, from the received plurality of frame signals; storing the data of each of the plurality of frame signals in a memory intermittently, using respective pulse widths of the plurality of synchronization signals as intervals, based on timing at which the plurality of synchronization signals are extracted; detecting timing at which data at a predetermined location in the frame signal is written to the memory, from the timing at which the plurality of synchronization signals are extracted; and reading data of each of the plurality of frame signals from the memory according to the detected timing.