A storage device and a storage system including the same are provided. The storage device includes a reference clock pin configured to receive a reference clock signal from a host, a reference clock frequency determination circuitry configured to determine a reference clock frequency from the reference clock signal received through the reference clock pin, and a device controller circuitry configured to perform a high speed mode link startup between the host and the storage device according to the reference clock frequency.

In a transmission circuit, a first pulse signal with a first frequency and a second pulse signal with a second frequency are output according to a rising edge and a falling edge of a first input signal, respectively. When a second input signal indicates an active level, the second pulse signal is output according to the falling edge of the first input signal and the second frequency is changed to a third frequency. In a reception circuit, a first level of a first output signal is changed to a second level according to a first induced signal via a transformer, the second level of the first output signal is changed to the first level according to a second induced signal via the transformer, and a second output signal is changed to an active level when a frequency of the second induced signal has changed to the third frequency.

In a transmission circuit, a first pulse signal with a first frequency and a second pulse signal with a second frequency are output according to a rising edge and a falling edge of a first input signal, respectively. When a second input signal indicates an active level, the second pulse signal is output according to the falling edge of the first input signal and the second frequency is changed to a third frequency. In a reception circuit, a first level of a first output signal is changed to a second level according to a first induced signal via a transformer, the second level of the first output signal is changed to the first level according to a second induced signal via the transformer, and a second output signal is changed to an active level when a frequency of the second induced signal has changed to the third frequency.

A sink device comprising a connector which has a first ground (GND) corresponding to a first standard; and a processor which receives a signal from a source device, via the connector, and if the received signal is of a second standard corresponding to a second GND that includes the first GND, requests, from the source device, information about the signal of the second standard.

A sink device comprising a connector which has a first ground (GND) corresponding to a first standard; and a processor which receives a signal from a source device, via the connector, and if the received signal is of a second standard corresponding to a second GND that includes the first GND, requests, from the source device, information about the signal of the second standard.

A signaling system is described. The signaling system comprises a transmit device, a receive device including a partial response receive circuit, and a signaling path coupling the transmit device and the receive device. The receive device observes an equalized signal from the signaling path, and includes circuitry to use feedback from the most recent previously resolved symbol to sample a currently incoming symbol. The transmit device equalizes transmit data to transmit the equalized signal, by applying weighting based on one or more data values not associated with the most recent previously resolved symbol value.

A control method of a distributed antenna system (DAS) including a baseband modem, according to one embodiment, may comprise the steps of: calculating frequency offsets for each RF path in the baseband modem; controlling an oscillator clock of a central unit (CU) on the basis of an average of the frequency offsets; determining an operation mode of the baseband modem; and controlling oscillator clocks of each distributed unit (DU) on the basis of the frequency offsets for each RF path when the operation mode of the baseband modem is a tracking mode.

The present disclosure relates to a signal processing device and an image display apparatus including the same. A signal processing device according to an embodiment of the present disclosure includes a sampler to downsample a baseband signal; a memory to store the downsampled data; a frequency shifter to read the data in the memory and shift the read data in a frequency domain; a symbol rate calculator to calculate a symbol rate based on the shifted data; a first offset calculator to calculate a first carrier frequency offset based on the calculated symbol rate; a second offset calculator to calculate a second carrier frequency offset based on the calculated first carrier frequency offset; and an offset compensator to compensate for the second carrier frequency offset. Accordingly, a time up to the demodulation completion may be shortened based on the baseband signal.

An optical receiver includes an APD that converts an input optical signal into a current signal, a TIA that converts the current signal output from the APD into a voltage signal, an LIA that shapes a waveform of the voltage signal output from the TIA, an AOC having a time constant switching function, the AOC automatically compensating for an offset voltage between differential outputs from the TIA, and a convergence-state detection circuit that outputs, after detecting convergence completion of the automatic compensation in the AOC, to the AOC, a time constant switching control signal for switching a time constant from a high-speed time constant to a low-speed time constant.

An optical receiver includes an APD that converts an input optical signal into a current signal, a TIA that converts the current signal output from the APD into a voltage signal, an LIA that shapes a waveform of the voltage signal output from the TIA, an AOC having a time constant switching function, the AOC automatically compensating for an offset voltage between differential outputs from the TIA, and a convergence-state detection circuit that outputs, after detecting convergence completion of the automatic compensation in the AOC, to the AOC, a time constant switching control signal for switching a time constant from a high-speed time constant to a low-speed time constant.