A multiplexer comprises: an output circuit comprising a multiplexer output; and a first buffer coupled to the output circuit and comprising: a first selection input configured to receive a first selection signal; a first logical input configured to receive a first logical input signal; and a first ground; wherein the multiplexer is configured to: couple the first logical input to the multiplexer output when the first selection signal is a first value; and couple the first logical input to the first ground when the first selection signal is a second value. A method comprises: receiving a selection signal and a first logical input signal; coupling a first logical input to a multiplexer output when the selection signal is a first value; and coupling the first logical input to a ground when the selection signal is a second value.

A multiplexer comprises: an output circuit comprising a multiplexer output; and a first buffer coupled to the output circuit and comprising: a first selection input configured to receive a first selection signal; a first logical input configured to receive a first logical input signal; and a first ground; wherein the multiplexer is configured to: couple the first logical input to the multiplexer output when the first selection signal is a first value; and couple the first logical input to the first ground when the first selection signal is a second value. A method comprises: receiving a selection signal and a first logical input signal; coupling a first logical input to a multiplexer output when the selection signal is a first value; and coupling the first logical input to a ground when the selection signal is a second value.

A digital television (DTV) receiving system includes an information detector, a resampler, a timing recovery unit, and a carrier recovery unit. The information detector detects a known data sequence which is periodically inserted in a digital television (DTV) signal received from a DTV transmitting system. The resampler resamples the DTV signal at a predetermined resampling rate. The timing recovery unit performs timing recovery on the DTV signal by detecting a timing error from the resampled DTV signal using the detected known data sequence. The carrier recovery unit performs carrier recovery on the resampled DTV signal by estimating a frequency offset value of the resampled DTV signal using the detected known data sequence.

A digital television (DTV) receiving system includes an information detector, a resampler, a timing recovery unit, and a carrier recovery unit. The information detector detects a known data sequence which is periodically inserted in a digital television (DTV) signal received from a DTV transmitting system. The resampler resamples the DTV signal at a predetermined resampling rate. The timing recovery unit performs timing recovery on the DTV signal by detecting a timing error from the resampled DTV signal using the detected known data sequence. The carrier recovery unit performs carrier recovery on the resampled DTV signal by estimating a frequency offset value of the resampled DTV signal using the detected known data sequence.

The present disclosure is directed to a system and method for measuring small frequency differences between two signals quickly and with high precision. In particular examples, an offset between two clock signals on a satellite can be accurately determined in a time period enabling rapid clock synchronization useful in position, navigation, and tracking (PNT) and satellite communications applications. The system and method may also be implemented in constellation of cooperative satellites or other space-borne and high-altitude assets, wherein a plurality of such assets are accurately time-synchronized and more accurate ensemble average calculations are enabled using two-way time transfer (TWTT) protocols. A particular application presently disclosed measurement and correction of very small frequency differences between an atomic clock signal and a tunable clock signal.

The present disclosure is directed to a system and method for measuring small frequency differences between two signals quickly and with high precision. In particular examples, an offset between two clock signals on a satellite can be accurately determined in a time period enabling rapid clock synchronization useful in position, navigation, and tracking (PNT) and satellite communications applications. The system and method may also be implemented in constellation of cooperative satellites or other space-borne and high-altitude assets, wherein a plurality of such assets are accurately time-synchronized and more accurate ensemble average calculations are enabled using two-way time transfer (TWTT) protocols. A particular application presently disclosed measurement and correction of very small frequency differences between an atomic clock signal and a tunable clock signal.

In some embodiments, a digital clock management system includes input signal conversion circuitry, logic circuitry and output signal conversion circuitry. The input signal conversion circuitry converts input signals to corresponding first digital data streams, each of which contains digital data synchronized to a first data clock. First digital logic circuitry converts the first digital data streams to second digital data streams, each of which contains digital data synchronized to the first data clock, and converts the second digital data streams to third digital data streams, each of which contains digital data synchronized to a common clock. Second digital logic circuitry converts the third digital data streams to a single digital data stream. The output signal conversion circuitry converts the single digital data stream to a modulated output signal.

In some embodiments, a digital clock management system includes input signal conversion circuitry, logic circuitry and output signal conversion circuitry. The input signal conversion circuitry converts input signals to corresponding first digital data streams, each of which contains digital data synchronized to a first data clock. First digital logic circuitry converts the first digital data streams to second digital data streams, each of which contains digital data synchronized to the first data clock, and converts the second digital data streams to third digital data streams, each of which contains digital data synchronized to a common clock. Second digital logic circuitry converts the third digital data streams to a single digital data stream. The output signal conversion circuitry converts the single digital data stream to a modulated output signal.

In one embodiment, an apparatus comprises: a receiver to receive training data from a transmitter; a clock and data recovery (CDR) circuit coupled to the receiver, the CDR circuit to recover a recovered clock signal from the training data; and a media access control (MAC) circuit coupled to the CDR circuit, wherein the MAC circuit is to send a clock switch indicator to the CDR circuit to cause the CDR circuit to halt tracking operation of the CDR circuit. Other embodiments are described and claimed.

In one embodiment, an apparatus comprises: a receiver to receive training data from a transmitter; a clock and data recovery (CDR) circuit coupled to the receiver, the CDR circuit to recover a recovered clock signal from the training data; and a media access control (MAC) circuit coupled to the CDR circuit, wherein the MAC circuit is to send a clock switch indicator to the CDR circuit to cause the CDR circuit to halt tracking operation of the CDR circuit. Other embodiments are described and claimed.