Described herein are systems and methods that provide for asymmetric image splitter image stream applications. In one embodiment, a system supporting image multi-streaming comprises an asymmetric image splitter engine that splits super-frame image streams into two or more image streams and a fractional clock divider circuit. The fractional clock divider may comprise a digital feedback control loop and a one-bit sigma delta modulator. The fractional clock divider circuit may provide compatible display clock frequencies for each of the two or more image streams. When a multi-image stream comprises the two image streams, the asymmetric image splitter engine adjusts a vertical asymmetry of a first image stream with a shortest height to same height as a second image stream by adding vertical padding to the first image stream. The super-frame image streams may comprise image streams from video, LIDAR, radar, or other sensors.

Described herein are systems and methods that provide for asymmetric image splitter image stream applications. In one embodiment, a system supporting image multi-streaming comprises an asymmetric image splitter engine that splits super-frame image streams into two or more image streams and a fractional clock divider circuit. The fractional clock divider may comprise a digital feedback control loop and a one-bit sigma delta modulator. The fractional clock divider circuit may provide compatible display clock frequencies for each of the two or more image streams. When a multi-image stream comprises the two image streams, the asymmetric image splitter engine adjusts a vertical asymmetry of a first image stream with a shortest height to same height as a second image stream by adding vertical padding to the first image stream. The super-frame image streams may comprise image streams from video, LIDAR, radar, or other sensors.

Certain aspects of the present disclosure relate to methods and apparatus for interference management with adaptive resource block (RB) allocation. In an exemplary method, a user equipment (UE) receives, from a base station (BS), an indication of a first set of resource blocks (RBs) to receive a first downlink (DL) transmission in a time interval, the UE receives, from the BS, an indication of a dynamically allocated second set of RBs to receive a second DL transmission from the BS in the time interval, and the UE alters one or more parameters of a receiver, based on the second set of RBs, when receiving the second DL transmission on the second set of RBs. Altering the one or more parameters may include switching a phase-locked loop (PLL) of the receiver to a center frequency determined based on the second set of RBs.

A receiving device includes a first sampling circuit extracting first binary data from a first signal based on a first edge timing of a first clock signal. The receiving device includes a second sampling circuit extracting second binary data from the first signal based on the first edge timing, and further extracting third binary data from the first signal based on a second edge timing of a second clock signal having a phase delayed from a phase of the first clock signal. The receiving device includes a circuit outputting a second signal indicating a phase shift direction of a third clock signal. The receiving device includes a circuit outputting waveform data based on the first binary data and the second binary data or the third binary data. The second sampling circuit selects either the second binary data or the third binary data based on the second signal.

A receiving device includes a first sampling circuit extracting first binary data from a first signal based on a first edge timing of a first clock signal. The receiving device includes a second sampling circuit extracting second binary data from the first signal based on the first edge timing, and further extracting third binary data from the first signal based on a second edge timing of a second clock signal having a phase delayed from a phase of the first clock signal. The receiving device includes a circuit outputting a second signal indicating a phase shift direction of a third clock signal. The receiving device includes a circuit outputting waveform data based on the first binary data and the second binary data or the third binary data. The second sampling circuit selects either the second binary data or the third binary data based on the second signal.

A clock and data recovery (CDR) system includes a correlator configured to receive data, determine a first value of the received data, and output a second value corresponding to the received data, an accumulator configured to generate an accumulation value by accumulating the second value output from the correlator and output the accumulation value, and a state machine configured to determine whether a repeating pattern is present in the CDR system based on the accumulation value.

A clock and data recovery (CDR) system includes a correlator configured to receive data, determine a first value of the received data, and output a second value corresponding to the received data, an accumulator configured to generate an accumulation value by accumulating the second value output from the correlator and output the accumulation value, and a state machine configured to determine whether a repeating pattern is present in the CDR system based on the accumulation value.

An adaptive line driver circuit configured to transmit a signal over a wired link includes a delay-locked loop (DLL) circuit, which includes a phase detector (PD) circuit, charge pump (CP) circuit, and voltage-controlled delay line (VCDL) circuit operatively coupled together. The delay-locked loop circuit provides pre-emphasis and feed-forward equalization of the signal. The delay locked loop circuit also provides a user-configurable parameter including at least one of pre-data tap amplitude, data tap amplitude, post-data tap amplitude, pre-data tap duration, post-data tap duration, pre-data tap quantity, and post-data tap quantity. The adaptive line driver circuit further includes a source-series terminated (SST) driver circuit operatively coupled to the delay-locked loop circuit.

The present disclosure discloses an on-chip synchronous self-repairing system based on a low-frequency reference signal. The system adopts a dual-input PLL stellate coupled structure or a dual-input PLL butterfly-shaped coupled structure, and delay of the whole loop is made to be an integral multiple of the reference signal by synchronizing the transmitted reference signal with the received reference signal, so as to ensure synchronization of local oscillation signal of each IC chip. The transmission wire based on an adjustable left-handed material is used as a delay wire to connect the dual-input PLL, thereby achieving low loss and reducing the physical distance of the delay wire. The system has the advantages of small area, low loss, strong adaptability and strict synchronization in various environments.

The present application provides a time synchronization method and an electronic device. The method includes sending a clock synchronization signal and first real time clock (RTC) information separately; and the clock synchronization signal is configured to measure a delay between a first module and at least one second module, the delay is used for phase compensation performed on the clock synchronization signal received at the side of the at least one second module, and the clock synchronization signal after being subjected to the phase compensation is configured to trigger the at least one second module to update local second RTC information to the first RTC information.