A method and system provides for execution of calibration cycles from time to time during normal operation of the communication channel. A calibration cycle includes de-coupling the normal data source from the transmitter and supplying a calibration pattern in its place. The calibration pattern is received from the communication link using the receiver on the second component. A calibrated value of a parameter of the communication channel is determined in response to the received calibration pattern. The steps involved in calibration cycles can be reordered to account for utilization patterns of the communication channel. For bidirectional links, calibration cycles are executed which include the step of storing received calibration patterns on the second component, and retransmitting such calibration patterns back to the first component for use in adjusting parameters of the channel at first component.

The Digital Time Processing using Rational Number Filters (DTP RNF) disclosed herein is contributing methods, systems and circuits for using a Precision Time Protocol (PTP) such as IEEE 1588 for distributing a master time secured by a master unit to slave units by utilizing slave clocks, synchronous to referencing frames communicated with PTP messages or compatible with them data receiver clocks, for maintaining a local slave time which is increased to a local master time by adding to it an estimate of a transmission delay derived by processing PTP messages or by other means, wherein such distribution of the master time includes filtering out phase noise of the timing referencing signals with the Rational Number Filters in order to produce accurate and stable timing implementing signals such as the slave clock, local slave time and local master time.

The Digital Time Processing using Rational Number Filters (DTP RNF) disclosed herein is contributing methods, systems and circuits for using a Precision Time Protocol (PTP) such as IEEE 1588 for distributing a master time secured by a master unit to slave units by utilizing slave clocks, synchronous to referencing frames communicated with PTP messages or compatible with them data receiver clocks, for maintaining a local slave time which is increased to a local master time by adding to it an estimate of a transmission delay derived by processing PTP messages or by other means, wherein such distribution of the master time includes filtering out phase noise of the timing referencing signals with the Rational Number Filters in order to produce accurate and stable timing implementing signals such as the slave clock, local slave time and local master time.

Proposed are an ultra-low jitter low-power phase-locked loop using a power-gating injection-locked frequency multiplier-based phase detector (PG-ILFM PD) and an operating method thereof. The proposed PG-ILFM PD includes a replica voltage controlled oscillator (R-VCO) configured to cut off the power supply of the R-VCO repeatedly based on a reference signal S.sub.REF and a fundamental sampling phase detector (FSPD) configured to receive an output signal S.sub.ILFM of the R-VCO as a reference signal for sampling and detect a phase error of a main voltage controlled oscillator (M-VCO).

Proposed are an ultra-low jitter low-power phase-locked loop using a power-gating injection-locked frequency multiplier-based phase detector (PG-ILFM PD) and an operating method thereof. The proposed PG-ILFM PD includes a replica voltage controlled oscillator (R-VCO) configured to cut off the power supply of the R-VCO repeatedly based on a reference signal S.sub.REF and a fundamental sampling phase detector (FSPD) configured to receive an output signal S.sub.ILFM of the R-VCO as a reference signal for sampling and detect a phase error of a main voltage controlled oscillator (M-VCO).

In an approach for a sparse information sharing system, a processor receives a request from a host owner for a host to become a server of an information sharing system, wherein the request specifies at least one type of information the server will maintain and provide to visitors of the server. A processor syncs the server with other servers of the information sharing system with information of the specified at least one type of information. A processor, responsive to the server receiving updated information from a visitor of the server, notifies the other servers of the updated information.

In one embodiment, a method receives a first time from a network device. The first time is derived from a first timing source in a first domain. The method receives a second time in a second domain from a second timing source. A difference time value is calculated between the first time and the second time. The method then sends the difference time value to the network device where the network device uses the difference time value to send a delay value to other computing devices to synchronize timing of the other computing devices in the second domain. The other computing devices are configured to synchronize the respective time using the delay value with mobile network devices to allow timing synchronization between the mobile network devices.

In one embodiment, a method receives a first time from a network device. The first time is derived from a first timing source in a first domain. The method receives a second time in a second domain from a second timing source. A difference time value is calculated between the first time and the second time. The method then sends the difference time value to the network device where the network device uses the difference time value to send a delay value to other computing devices to synchronize timing of the other computing devices in the second domain. The other computing devices are configured to synchronize the respective time using the delay value with mobile network devices to allow timing synchronization between the mobile network devices.

A data transfer circuit (40) according to the invention includes a memory (41) configured to write data in accordance with a write pointer in synchronization with a first clock, and read out the data in accordance with a readout pointer in synchronization with a second clock, a clock generation circuit (44) configured to generate the second clock by multiplying a reference clock by a rational number N, a frequency error estimation circuit (42) configured to estimate a frequency error between the first clock and the second clock based on a change amount of a pointer difference between the write pointer and the readout pointer, and an adjustment circuit (43) configured to output, as an adjustment multiple ΔN, a value obtained by dividing the estimated frequency error by a frequency of the reference clock. The clock generation circuit (44) generates the second clock by multiplying the reference clock by a rational number (N+ΔN) using the adjustment multiple ΔN output from the adjustment circuit (43). A data transfer circuit capable of speeding up clock synchronization can be provided.

Disclosed herein are related to systems and methods for correcting non-linearity due to duty cycle error. In one aspect, a system includes a mixer configured to up-convert transmission (Tx) data, a coefficient calibrator configured to select a target value of a coefficient based on a measurement of an interference signal due to non-linearity of the mixer, and an interference canceller coupled to the coefficient calibrator and the mixer. In some embodiments, the interference canceller is configured to generate compensated Tx data based on the Tx data and the selected target value of the coefficient and provide the compensated Tx data to the mixer. In some embodiments, the compensated Tx data corrects for the non-linearity of the mixer.