This application relates to the field of communication technologies, and discloses a communication method and apparatus. On example method includes: a backscatter device receives an excitation signal from an exciter. The backscatter device determines a backscatter signal pattern in a backscatter signal pattern set, where the backscatter signal pattern set includes a plurality of backscatter signal patterns, and backscatter reference signals in the plurality of backscatter signal patterns do not overlap in time domain. The backscatter device modulates a backscatter reference signal and a backscatter data signal on the excitation signal based on the determined backscatter signal pattern, to obtain a backscatter signal. The backscatter device sends the backscatter signal to a receiver.

An aspect relates to an apparatus including an input buffer including an input configured to receive an input voltage; a ramp voltage generator including an input coupled to an output of the input buffer; an evaluation circuit including an input coupled to an output of the ramp voltage generator, wherein the evaluation circuit includes a first resistor coupled in series with first field effect transistor (FET) between a first voltage rail and a second voltage rail; and an output buffer including an input coupled to a drain of the first FET and an output configured to generate an output voltage.

The present invention discloses a transceiver apparatus having phase-tracking mechanism. A phase detection circuit of a receiver circuit performs sampling and phase detection on an input data signal according to a sampling clock signal to generate a phase detection result. A proportional gain circuit of the receiver circuit applies a proportional gain operation on the phase detection result to generate a phase adjusting signal. A CDR circuit of the receiver circuit receives a source clock signal to generate the sampling clock signal and performs phase-adjusting according to the phase adjusting signal. The integral gain circuit apples an integral gain operation on the phase detection result to generate a frequency adjusting signal. The source clock generating circuit receives a reference clock signal to generate the source clock signal and perform frequency-adjusting according to the frequency adjusting signal. The transmitter circuit performs signal transmission according to the source clock signal.

The present invention discloses a transceiver apparatus having phase-tracking mechanism. A phase detection circuit of a receiver circuit performs sampling and phase detection on an input data signal according to a sampling clock signal to generate a phase detection result. A proportional gain circuit of the receiver circuit applies a proportional gain operation on the phase detection result to generate a phase adjusting signal. A CDR circuit of the receiver circuit receives a source clock signal to generate the sampling clock signal and performs phase-adjusting according to the phase adjusting signal. The integral gain circuit apples an integral gain operation on the phase detection result to generate a frequency adjusting signal. The source clock generating circuit receives a reference clock signal to generate the source clock signal and perform frequency-adjusting according to the frequency adjusting signal. The transmitter circuit performs signal transmission according to the source clock signal.

A PAM-4 receiver with jitter compensation clock and data recovery is provided. The receiver includes a first-order delay-locked loop (DLL) which employs a bang-bang phase detector (BBPD) and a voltage-controlled delay line (VCDL) circuit supporting 40 MHz jitter tracking bandwidth and static phase skew elimination. A second-order wideband phase-locked loop (WBPLL) using the ¼-rate reference clock provides multi-phase clock generation with low input-to-output latency. To suppress the consequent jitter transfer, a jitter compensation circuit (JCC) acquires the jitter transfer amplitude and frequency information by detecting the DLL loop filter voltage (VLF(s)) signal, and generates an inverted loop filter voltage signal, denoted as VLF.sub.INV(s). The VLF.sub.INV(S) modulates a group of complementary VCDLs (C-VCDLs) to attenuate the jitter transfer on both recovered clock and data. With the provided receiver, a jitter compensation ratio up to 60% can be supported from DC to 4 MHz, with a −3-dB corner frequency of 40 MHz.

Embodiments of the present disclosure describe mechanisms for radio frequency (RF) ranging between pairs of radio units based on radio signals exchanged between units. An exemplary radio system may include a first radio unit, configured to transmit a first radio signal, and a second radio unit configured to receive the first radio signal, adjust a reference clock signal of the second radio unit based on the first radio signal, and transmit a second radio signal generated based on the adjusted reference clock signal. Such a radio system may further include a processing unit for determining a distance between the first and second radio units based on a phase difference between the first radio signal as transmitted by the first radio unit and the second radio signal as received at the first radio unit. Disclosed mechanisms may enable accurate RF ranging using low-cost, low-power radio units.

An equalizer circuit, a method for sampling data and a memory are provided. The equalizer circuit includes a first input buffer circuit, a second input buffer circuit and a selecting and sampling circuit. The first input buffer circuit and the second input buffer circuit are respectively connected with the selecting and sampling circuit, and reference voltages used in the first input buffer circuit and the second input buffer circuit are different from each other. The selecting and sampling circuit selects to perform data sampling on a data signal outputted by the first input buffer circuit or the second input buffer circuit according to data outputted previously by the equalizer circuit, and takes sampled data as data outputted currently by the equalizer circuit.

Systems and methods related to charge locking circuits and a control system for qubits are provided. A system for controlling qubit gates includes a first packaged device comprising a quantum device including a plurality of qubit gates, where the quantum device is configured to operate at a cryogenic temperature. The system further includes a second packaged device comprising a control circuit configured to operate at the cryogenic temperature, where the first packaged device is coupled to the second packaged device, and where the control circuit comprises a plurality of charge locking circuits, where each of the plurality of charge locking circuits is coupled to at least one qubit gate of the plurality of qubit gates via an interconnect such that each of the plurality of charge locking circuits is configured to provide a voltage signal to at least one qubit gate.

The present disclosure provides an analytical framework to investigate judicious topology reweighting of radio networks of clocks, when distributed time transfer and synchronization are based on physical layers and subject to the presence of false timing signals. Protagonist clocks exchange timing information pairwise, which is modeled as clocks tending to follow the majority of their neighbors. Antagonist clocks inject false timing signals, thereby, influencing the timing synchronization of (some of) the other protagonist clocks they meet. A class of pursuit-evasion graphical games subject to complete state observations and exploitation of phase noise disturbances, is proposed in designing clock steering protocols for resilient time metrologies that will be immune to erroneous timing signals injected into remote time dissemination networks.

A method for recovering the symbol time by a receiver to decode a sequence of symbols transmitted by a transmitter when the symbol time of the transmitter is biased with respect to the symbol time of the receiver. When a transition is detected between two consecutive symbols, an absolute error on the instant of the current symbol is measured and a statistical model of the bias is updated. A correction may then be applied to the instants of the subsequent symbols depending on the measured absolute error and/or a bias estimated from the statistical model. During periods in which there are no transitions between symbols, an absolute error cannot be measured, but it is still possible to apply a correction to the instants of the subsequent symbols depending on a relative error extrapolated from the statistical model.