H04L7/041

METHOD AND APPARATUS FOR GENERATING STANDARD PATTERN FOR DATA SIGNALS

Methods and apparatus for generating a standard pattern for data signals from a set of multiple data signals are provided. The standard pattern consists of a signal length, a centerline, an upper limit, and a lower limit. One of methods comprises, receiving first and second data signals, determining a standard pattern length for each of the first and second data signals, sampling each of the first and second data signals by as much as the determined standard pattern length, aligning the sampled first and second data signals, and generating a standard pattern for the first and second data signals by overlapping the aligned first and second data signals, wherein the generated standard pattern is a standard pattern having reflected thereinto upper and lower limit ranges that are determined using levels of the aligned first and second data signals.

ADAPTIVE EQUALIZATION USING CORRELATION OF DATA PATTERNS WITH ERRORS
20210399929 · 2021-12-23 ·

An integrated receiver supports adaptive receive equalization. An incoming bit stream is sampled using edge and data clock signals derived from a reference clock signal. A phase detector determines whether the edge and data clock signals are in phase with the incoming data, while some clock recovery circuitry adjusts the edge and data clock signals as required to match their phases to the incoming data. The receiver employs the edge and data samples used to recover the edge and data clock signals to note the locations of zero crossings for one or more selected data patterns. The pattern or patterns may be selected from among those apt to produce the greatest timing error. Equalization settings may then be adjusted to align the zero crossings of the selected data patterns with the recovered edge clock signal.

Receiving apparatus, receiving method, computer readable medium storing receiving program, and manufacturing method
11196536 · 2021-12-07 · ·

A receiving apparatus is provided, including: a receiving unit to receive a plurality of pulses including a synchronization pulse and a data pulse having a data pulse width corresponding to a data value; a searching unit to search for pulse information indicating a pulse period or the like that falls within a synchronization pulse acceptable range from among pulse information indicating pulse periods or pulse widths of the respective pulses; a detecting unit to detect whether pulse information of a second pulse at a predetermined location relative to a first pulse corresponding to the searched pulse information indicates a pulse period or the like that falls within a data pulse acceptable range; an identifying unit to identify the first pulse as the synchronization pulse on condition that the pulse information of the second pulse indicates a pulse period or the like that falls within the data pulse acceptable range.

One way ranging measurement using sounding sequence

A system and method for one-way ranging is disclosed. The system comprises a transmitter, also referred to as a tag, transmitting a packet having a sounding sequence. The receiver, also referred to as the locator, receives the sounding sequence. The receiver measures and saves the phase at a plurality of points in time. The sounding sequence has two frequencies, which are additive inverses of one another. A discrete Fourier transform is performed on the plurality of phase measurements to determine the phase of each of the two frequencies. The difference between these two frequencies is related to the time that the packet traveled. Additionally, a calibration of the transmit path and/or receive path may be performed to improve the accuracy of the results.

Error-tolerant forward error correction ordered set message decoder
11356197 · 2022-06-07 · ·

Methods are described for identifying and acting upon predetermined message patterns during reception of a data stream structured as USB message frames. A first embodiment performs pattern matching between received message bits and one or more predetermined sequences, identifying unscrambled ordered set messages. A second embodiment applies a descrambling operation and performs comparable pattern matching between descrambled received message bits and one or more additional predetermined sequences, identifying scrambled ordered set messages.

RADIO COMMUNICATION APPARATUS AND RADIO COMMUNICATION METHOD
20220174619 · 2022-06-02 · ·

A radio communication apparatus makes it possible to prevent contents of communication from being intercepted. The radio communication apparatus includes a generation unit configured to generate a first unique word based on operation time information of the radio communication apparatus before communication with a radio communication apparatus is started, and generate, for each radio frame, an ith unique word (i: an integer equal to or greater than two) based on an (i-1)th unique word when the communication is started, and a transmitting unit configured to transmit a first radio frame including the first unique word and an ith radio frame including the ith unique word to the radio communication apparatus.

METHODS FOR NANOSECOND-SCALE TIME SYNCHRONIZATION OVER A NETWORK

A method includes, at a first node: transmitting a first synchronization signal at a first time according to a first clock of the first node; back-coupling the first synchronization signal to generate a first self-receive signal; calculating a time-of-arrival of the first self-receive signal according to the first clock; and calculating a time-of-arrival of the second synchronization signal according to the first clock. The method also includes, at the second node: transmitting the second synchronization signal at a second time according to a second clock of the second node; back-coupling the second synchronization signal to generate a second self-receive signal; calculating a time-of-arrival of the second self-receive signal according to the second clock; and calculating a time-of-arrival of the first synchronization signal according to the second clock. The method S100 further includes calculating a time bias and a propagation delay between the pair of nodes based on the time-of-arrivals.

Authenticated confirmation and activation message

A data transmitter for transmitting data to a data receiver is provided, wherein individual communication information is known to the data transmitter and the data receiver, the data transmitter being configured to generate an individual synchronization sequence while using the individual communication information.

Signal sending device, signal receiving device, symbol timing synchronization method, and system

The present disclosure relates to the field of wireless communications technologies, relates to a signal sending device, a signal receiving device, a symbol timing synchronization method, and a system, and resolves a problem that complexity of symbol timing synchronization performed by a terminal with relatively low crystal oscillator accuracy is high. In a receiving device, a receiving module receives a synchronization signal including a first signal and a second signal. The first signal includes N1 generalized ZC sequences, and the second signal includes N2 generalized ZC sequences. The second signal is used to distinguish different cells or different cell groups. There are at least two generalized ZC sequences with different root indexes in (N1+N2) generalized ZC sequences. A processing module performs a first sliding correlation operation and a second sliding correlation operation on the synchronization signal, and performs symbol timing synchronization according to a relationship between a sliding correlation peak generated when a sliding correlation is performed on the N1 generalized ZC sequences and a sliding correlation peak generated when a sliding correlation is performed on the N2 generalized ZC sequences. This has relatively low implementation complexity, compared with an existing method in which grid search should be performed multiple times to compensate for a relatively large phase rotation.

Clock recovery

Clock recovery from a serial data signal involves using a serializer/deserializer (SERDES) to produce a clock signal which periodically alternates between high and low output clock values. These high and low clock values are generated by outputting for each clock period a series of N digital bits including a plurality of low-level bits to form each low output clock value and a plurality of high-level bits to form each high output clock value. A sync pulse obtained from a sync word present in each frame of the serial data signal is used to periodically determine a frequency error of the clock signal. The frequency error is used as a basis to change a phase of the adjusted clock signal responsive to the frequency error.