Embodiments of this application disclose a data processing method, which can be applied to a clock synchronization network system. The system can correct, based on a clock frequency error or a time error, a data timestamp of a data packet collected by the system in a time period in which there is no reference clock, so that a corrected system time of the data packet is consistent with a reference time. This improves accuracy of data record.

Communication systems and methods in accordance with various embodiments of the invention utilize modulation on zeros. Carrier frequency offsets (CFO) can result in an unknown rotation of all zeros of a received signal's z-transform. Therefore, a binary MOCZ scheme (BMOCZ) can be utilized in which the modulated binary data is encoded using a cycling register code (e.g. CPC or ACPC), enabling receivers to determine cyclic shifts in the BMOCZ symbol resulting from a CFO. Receivers in accordance with several embodiments of the invention include decoders capable of decoding information bits from received discrete-time baseband signals by: estimating a timing offset for the received signal; determining a plurality of zeros of a z-transform of the received symbol; identifying zeros from. the plurality of zeros that encode received bits by correcting fractional rotations resulting from the CFO; and decoding information bits based upon the received bits using a cycling register code.

An input signal arranged in frames is received. The frames include a cyclic redundancy check (CRC) field including a number of bits having bit edges. A timing signal is generated to include adjustable duration waveforms at one of a first duration value and a second duration value. A CRC check determines the occurrence, over the duration, of a number of waveforms of the timing signal having their duration adjusted to one of the first duration value and the second duration value which corresponds to the number of bits. A check signal is produced having a pass/fail value. If pass, the duration of the waveforms in the timing signal is maintained adjusted to the one of the first duration value and the second duration value. If fail, the duration of the waveforms in the timing signal is re-adjusted to the other of the first duration value and the second duration value.

A communication system comprising a light source associated with a first item of interest; a visible light communications system operably coupled to the light source of the first item of interest, the visible light communications system configured to process information as an encoded signal and output the encoded signal via the light source; and a receiver associated with a second item of interest, the receiver configured to receive the encoded signal from the light source and process the encoded signal to obtain the information.

Methods of guaranteed reception and of processing of a digital signal in an avionics system comprise a plurality of computers, each computer comprising processing electronics and a software layer, which, on receipt of an event, carries out the following steps: at a first instant, sending to each of the other computers of a first signal (ACK) of reception of the event; at a second instant termed “TimeOut ACK”, if the electronic computer has not received one of the first signals emanating from one of the other computers, sending of a second failure signal (FAIL) to each of the other computers; at a third instant termed “TimeOut GARANTEED”, if a second failure signal has been received by the computer, absence of taking into account of the event by the computer and if no failure signal has been received by the computer, taking into account of the event by the data processing electronics of the computer.

In one implementation, a receiver has a module to calculate the cross-correlation between a portion of a digital representation of a received signal and a reference signal. The receiver also has a module to generate an estimate of a portion of a message potentially included in the digital representation of the received signal and a screening module to determine the likelihood that the received signal includes a message. For a received signal that is determined likely to include a message, the receiver includes a carrier refinement module to shift the frequency of carrier pulses in the digital representation of the received signal toward a desired frequency and to align the phase of carrier pulses in the digital representation of the received signal with a desired phase and a coherent matched filter to recover the message from the digital representation of the received signal.

Systems and methods are provided for enabling reliable signaling in the presence of strong phase noise and frequency offset. To this end, a method is provided comprising receiving, at a receiver, a communication signal, including data, from a transmitter via a communication channel, and jointly tracking and jointly correcting phase noise errors and frequency errors in the communication signal with a joint detector using an iterative feedback correction process between an output decoder of the receiver and the joint detector.

A communication device includes a sampler configured to sample an input signal, wherein the sampler is configured to generate a sampled value for each sampling time of a sequence of sampling times, a sequence value generator configured to generate an output value for each sampling time of the sequence of sampling times based on the sampled values, wherein the sequence value generator is configured to set the output value for a sampling time based on the sampled value for the sampling time and based on a limitation of the difference between the output value for the sampling time and the output value for the preceding sampling time in the sequence of sampling times, and an edge detector configured to detect an edge in the input signal based on the output values.

A wireless receiver is disclosed. The wireless receiver includes a phased array antenna panel having a plurality of antennas, and a low resolution analog-to-digital (A/D) converter coupled to each of the plurality of antennas, where the low resolution A/D converter is configured to provide a digital output based on comparing a reference value with a sum of noise value and signal value of an analog input received by the corresponding one of the plurality of antennas. Noise signals received by the plurality of antennas are uncorrelated, and a signal to noise ratio (SNR) of the analog input can be less than one. The low resolution A/D converter can be a one-bit A/D converter. The one-bit A/D converter can be a comparator receiving the sum of noise value and signal value as one comparator input, and receiving the reference value as another comparator input.

A display is disclosed where in an optimization mode, the controller transmits a first lock signal having a pulse waveforms to a first source driver circuit among source driver circuits, receives a second lock signal having pulse waveforms from a last source driver circuit that receives the first lock signal, and transmits phase loop fixed data for recovering a frequency and a phase of a clock to each of the source driver circuits when the second lock signal is received, and in the display mode, the controller transmits a first lock signal having a preset voltage level to the first source driver circuit, receives a second lock signal having a plurality of preset voltage levels from a last source driver circuit, and supplies an image signal and control data to each of the source driver circuits when the second lock signal is received.