A timing lock identification method is provided according to an embodiment of the disclosure. The method includes: generating one or more first phase adjustment pulses and one or more second phase adjustment pulses by a timing recovery circuit, where the one or more first phase adjustment pulses are configured to increase a phase of an output signal of an oscillator, and the one or more second phase adjustment pulses are configured to decrease the phase of the output signal; and obtaining a difference value between the number of the one or more first phase adjustment pulses and the number of the one or more second phase adjustment pulses in a detection window and determining whether the timing recovery circuit reaches a locking state of timing recovery according to the difference value. Furthermore, a signal receiving circuit is provided according to an embodiment of the disclosure.

This application relates to a codeword synchronization method, a chip, a network device, and a system. The codeword synchronization method includes: receiving a first data sequence, where the first data sequence includes a plurality of bits, and a codeword in the first data sequence includes extension information for verifying the codeword; selecting at least one group of bits from the plurality of bits as the extension information to perform verification, and determining a candidate bit in the plurality of bits based on a result of the verification; and determining a synchronization position based on the candidate bit, where the synchronization position indicates a start position of the codeword that is in the first data sequence.

A data processing method, a data transmit end, and a data receive end are presented. The data processing method includes inserting multiple alignment markers (AMs) into a first data stream, where the first data stream is a data stream that is transcoded and scrambled after being encoded at a physical layer; adaptively allocating the first data stream that includes the AMs to multiple physical coding sublayer (PCS) lanes to obtain second data streams; performing forward error correction (FEC) encoding on the second data streams on the multiple PCS lanes to obtain third data streams; and delivering the third data streams to multiple physical medium attachment sublayer (PMA) lanes according to an input bit width of a Serdes to obtain multiple fourth data streams, each fourth data stream includes at least one complete and continuous AM, and the at least one AM is an AM in the multiple AMs.

A communication device includes a receiver configured to receive a signal, a sampler configured to sample the signal for each digital value of the predefined sequence of digital values in the signal, a memory configured to store a table giving, for each of a plurality of combinations of one or more preceding first digital values and a following second digital value, a threshold for a signal level to detect the second digital value, an initializer configured to, for a combination in a subset of the plurality of combinations, initialize the table based on a sample of the signal for the second value, and for a combination outside of the subset, select a combination from the subset and initialize the table based on a sample of the signal for the second value of the selected combination.

In one embodiment, a method receives a first time from a network device. The first time is derived from a first timing source in a first domain. The method receives a second time in a second domain from a second timing source. A difference time value is calculated between the first time and the second time. The method then sends the difference time value to the network device where the network device uses the difference time value to send a delay value to other computing devices to synchronize timing of the other computing devices in the second domain. The other computing devices are configured to synchronize the respective time using the delay value with mobile network devices to allow timing synchronization between the mobile network devices.

A recording apparatus is provided. An adjustment unit executes adjustment processing for adjusting a delay amount of a timing signal. An input control unit executes input control to input continuously recording target data to be recorded to a storage medium, to a buffer memory. A recording control unit executes recording control for recording the recording target data held in the buffer memory to the storage medium, using an input/output unit configured to receive data from the storage medium according to the timing signal. A control unit performs control such that the input control is started before a recording start instruction and the recording control is started in response to the recording start instruction, and such that the adjustment processing is executed during execution of the input control and before the recording control is started in response to the recording start instruction.

A frame synchronization method of an embodiment is disclosed. The method includes comparing a preamble arranged at a predetermined position in a received signal with a predetermined signal pattern to calculate a maximum preamble correlation value, using the maximum preamble correlation value to estimate a C/N ratio of the received signal, setting a correlation threshold for frame synchronization detection according to the estimated C/N ratio, and comparing an access address arranged at a predetermined position in the received signal with a predetermined signal pattern to calculate a preamble correlation value, and detecting timing at which the preamble correlation value first exceeds the set correlation threshold as a frame synchronization point.

A clock data recovery (CDR) apparatus can include an interpolator circuitry to interpolate an input received signal and to generate an output signal removing the sampling clock offsets. The apparatus can include timing error detector (TED) circuitry coupled to process the output signal and to provide a timing error as feedback to the interpolator circuitry, the timing error being adjusted by gain factors used in at least one of an automatic gain control (AGC) circuitry and an orthogonalization circuitry. The apparatus can include loop filter (LF) circuitry to filter the timing error to remove noise effects. The apparatus can include numerically controlled oscillator (NCO) circuitry to adjust for a basepoint and fractional interval used to adjust resampling coefficients within the interpolator circuitry.

A frame synchronization method of an embodiment is disclosed. The method includes comparing a preamble arranged at a predetermined position in a received signal with a predetermined signal pattern to calculate a maximum preamble correlation value, using the maximum preamble correlation value to estimate a C/N ratio of the received signal, setting a correlation threshold for frame synchronization detection according to the estimated C/N ratio, and comparing an access address arranged at a predetermined position in the received signal with a predetermined signal pattern to calculate a preamble correlation value, and detecting timing at which the preamble correlation value first exceeds the set correlation threshold as a frame synchronization point.

An apparatus is provided which comprises: a first circuitry to track a spread spectrum of a differential signal according to sampled data; and a second circuitry to adjust phase of a clock according to the spread spectrum, wherein the clock is used for sampling the differential signal.