Patent classifications
H04L7/06
METHOD AND APPARATUS FOR CARRIER FREQUENCY-OFFSET DETERMINATION AND STORAGE MEDIUM
A method and an apparatus for carrier frequency-offset determination and a storage medium are provided. The method includes the following. A first carrier initial frequency-offset is obtained according to a pilot time interval and a pilot phase difference of a first carrier. A second carrier frequency-offset is obtained according to a carrier frequency-ratio of a second carrier to the first carrier and the first carrier initial frequency-offset. A first carrier frequency-offset is obtained according to the first carrier initial frequency-offset.
METHOD AND APPARATUS FOR CARRIER FREQUENCY-OFFSET DETERMINATION AND STORAGE MEDIUM
A method and an apparatus for carrier frequency-offset determination and a storage medium are provided. The method includes the following. A first carrier initial frequency-offset is obtained according to a pilot time interval and a pilot phase difference of a first carrier. A second carrier frequency-offset is obtained according to a carrier frequency-ratio of a second carrier to the first carrier and the first carrier initial frequency-offset. A first carrier frequency-offset is obtained according to the first carrier initial frequency-offset.
Image display system and image data transmission apparatus and method thereof having synchronous data transmission mechanism
The present invention discloses an image data transmission apparatus. The lock confirmation circuit receives an original signal having an original pulse width from the image data reception apparatus to generate an output signal. The image data transmission circuit determines that the image data reception apparatus locks a transmission frequency when an output pulse width is larger than a pulse threshold value to perform a synchronous image data transmission. The lock confirmation circuit sets the output pulse width to be a lengthened pulse width when a difference between the original pulse width and the pulse threshold value is smaller than a predetermined value and the original pulse width is not smaller than the pulse threshold value. The lock confirmation circuit sets the output pulse width to be a shortened pulse width when the difference is smaller than the predetermined value and the original pulse width is smaller than the pulse threshold value.
Image display system and image data transmission apparatus and method thereof having synchronous data transmission mechanism
The present invention discloses an image data transmission apparatus. The lock confirmation circuit receives an original signal having an original pulse width from the image data reception apparatus to generate an output signal. The image data transmission circuit determines that the image data reception apparatus locks a transmission frequency when an output pulse width is larger than a pulse threshold value to perform a synchronous image data transmission. The lock confirmation circuit sets the output pulse width to be a lengthened pulse width when a difference between the original pulse width and the pulse threshold value is smaller than a predetermined value and the original pulse width is not smaller than the pulse threshold value. The lock confirmation circuit sets the output pulse width to be a shortened pulse width when the difference is smaller than the predetermined value and the original pulse width is smaller than the pulse threshold value.
Communication unit and method for clock distribution and synchronization
A communication unit (300) is described that includes a plurality of cascaded devices that includes at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device comprises a modulator circuit (362) configured to: receive a system clock signal and a frame start signal; modulate the system clock signal with the frame start signal to produce a modulated master-slave clock signal (384); and transmit the modulated master-slave clock signal (384) to the at least one slave device. The at least one slave device comprises a demodulator circuit (364) configured to: receive and demodulate the modulated master-slave clock signal (384); and re-create therefrom the system clock signal (388, 385) and the frame start signal (390, 386).
BAUD-RATE CLOCK RECOVERY LOCK POINT CONTROL
A baud-rate phase detector uses two error samplers. One error sampler is used to determine whether the sampling time is too early error detection. The other is used to determine whether sampling time is too late. The early error sampler is configured to use a first threshold voltage. The late error sampler is configured to use a second threshold voltage. By adjusting the voltage difference between the first threshold voltage and the second threshold voltage, the phase difference between the local timing reference clock and the transitions of the data signal may be adjusted. The phase difference between the local timing reference clock and the transitions of the data signal may be adjusted to improve or optimize a desired receiver characteristic such as bit error rate or signal eye opening.
BAUD-RATE CLOCK RECOVERY LOCK POINT CONTROL
A baud-rate phase detector uses two error samplers. One error sampler is used to determine whether the sampling time is too early error detection. The other is used to determine whether sampling time is too late. The early error sampler is configured to use a first threshold voltage. The late error sampler is configured to use a second threshold voltage. By adjusting the voltage difference between the first threshold voltage and the second threshold voltage, the phase difference between the local timing reference clock and the transitions of the data signal may be adjusted. The phase difference between the local timing reference clock and the transitions of the data signal may be adjusted to improve or optimize a desired receiver characteristic such as bit error rate or signal eye opening.
Synchronization Signal (Sync Mark) Detection Using Multi-Frequency Sinusoidal (MFS) Signal-Based Filtering
Novel tools and techniques are provided for implementing synchronization signal (“Sync Mark”) detection using multi-frequency sinusoidal (“MFS”) signal-based filtering. In various embodiments, a computing system may detect a location of a Sync Mark within a data signal, by using MFS signal-based filtering and a sliding window comprising successive search windows each having a bit length corresponding to a bit length of the Sync Mark to identify a portion of the data signal having a magnitude indicative of the Sync Mark. The computing system may refine the location of the Sync Mark within the data signal, by performing a phase measurement on the identified portion of the data signal having the magnitude indicative of the Sync Mark to identify a sub-portion of the identified portion of the data signal, the identified sub-portion having a phase indicative of the Sync Mark, the phase measurement being performed based on the MFS signal-based filtering.
Synchronization Signal (Sync Mark) Detection Using Multi-Frequency Sinusoidal (MFS) Signal-Based Filtering
Novel tools and techniques are provided for implementing synchronization signal (“Sync Mark”) detection using multi-frequency sinusoidal (“MFS”) signal-based filtering. In various embodiments, a computing system may detect a location of a Sync Mark within a data signal, by using MFS signal-based filtering and a sliding window comprising successive search windows each having a bit length corresponding to a bit length of the Sync Mark to identify a portion of the data signal having a magnitude indicative of the Sync Mark. The computing system may refine the location of the Sync Mark within the data signal, by performing a phase measurement on the identified portion of the data signal having the magnitude indicative of the Sync Mark to identify a sub-portion of the identified portion of the data signal, the identified sub-portion having a phase indicative of the Sync Mark, the phase measurement being performed based on the MFS signal-based filtering.
Method for precise timestamping of narrowband signals in the presence of multipath
A method for detecting times-of-arrival of signals comprising, at a receiving node: during a time slot, receiving a signal comprising a carrier signal characterized by a carrier frequency and modulated by a template signal defining a code sequence characterized by a transmitter chip period; demodulating the signal according to a local oscillator frequency to generate a received baseband signal, the local oscillator frequency and the carrier frequency defining a desynchronization ratio characterized by a denominator greater than a threshold denominator; sampling the received baseband signal at the transmitter chip period to generate a set of digital samples; generating a reconstructed baseband signal based on the set of digital samples; calculating a cross-correlation function comprising a cross-correlation of the reconstructed baseband signal and the template signal; and calculating, on the fine time grid, a time-of-arrival of the signal based on the cross-correlation function.