A method for detecting times-of-arrival of signals comprising, at a receiving node: during a time slot, receiving a signal comprising a carrier signal characterized by a carrier frequency and modulated by a template signal defining a code sequence characterized by a transmitter chip period; demodulating the signal according to a local oscillator frequency to generate a received baseband signal, the local oscillator frequency and the carrier frequency defining a desynchronization ratio characterized by a denominator greater than a threshold denominator; sampling the received baseband signal at the transmitter chip period to generate a set of digital samples; generating a reconstructed baseband signal based on the set of digital samples; calculating a cross-correlation function comprising a cross-correlation of the reconstructed baseband signal and the template signal; and calculating, on the fine time grid, a time-of-arrival of the signal based on the cross-correlation function.

In a case where signals branched from a single reference signal source are transmitted via a plurality of cables, a phase synchronization circuit can be used to stabilize a phase of a signal to be outputted from each cable. However, the phases of signal to be outputted from each cable is affected by combination of a length of each cable and an amount of delay caused by feedback control, so that phases of synchronization signals to be outputted from a plurality of transmission paths are not always the same as each other. In the present invention, since a frequency multiplier that multiplies a frequency of a signal outputted from each transmission path by an even number is provided for a phase synchronization circuit, the phases of the synchronization signals to be outputted from the transmission paths are aligned even when signals are branched from one reference signal.

In a case where signals branched from a single reference signal source are transmitted via a plurality of cables, a phase synchronization circuit can be used to stabilize a phase of a signal to be outputted from each cable. However, the phases of signal to be outputted from each cable is affected by combination of a length of each cable and an amount of delay caused by feedback control, so that phases of synchronization signals to be outputted from a plurality of transmission paths are not always the same as each other. In the present invention, since a frequency multiplier that multiplies a frequency of a signal outputted from each transmission path by an even number is provided for a phase synchronization circuit, the phases of the synchronization signals to be outputted from the transmission paths are aligned even when signals are branched from one reference signal.

The present application provides a time synchronization method and an electronic device. The method includes sending a clock synchronization signal and first real time clock (RTC) information separately; and the clock synchronization signal is configured to measure a delay between a first module and at least one second module, the delay is used for phase compensation performed on the clock synchronization signal received at the side of the at least one second module, and the clock synchronization signal after being subjected to the phase compensation is configured to trigger the at least one second module to update local second RTC information to the first RTC information.

The present application provides a time synchronization method and an electronic device. The method includes sending a clock synchronization signal and first real time clock (RTC) information separately; and the clock synchronization signal is configured to measure a delay between a first module and at least one second module, the delay is used for phase compensation performed on the clock synchronization signal received at the side of the at least one second module, and the clock synchronization signal after being subjected to the phase compensation is configured to trigger the at least one second module to update local second RTC information to the first RTC information.

A method for performing pattern detection and alignment on a programmable logic device is disclosed. A word aligner unit, implemented by a hard intellectual property block, is configured to detect a plurality of control characters by recognizing a proper subset of bits that are common among the plurality of control characters. It is determined whether a predetermined number of consecutive control characters has been detected in a frame of data. A boundary location associated with a detected predetermined number of consecutive control characters from the word aligner unit is identified. The frame of data is aligned in response to the boundary location associated with the detected predetermined number of consecutive control characters.

A method for performing pattern detection and alignment on a programmable logic device is disclosed. A word aligner unit, implemented by a hard intellectual property block, is configured to detect a plurality of control characters by recognizing a proper subset of bits that are common among the plurality of control characters. It is determined whether a predetermined number of consecutive control characters has been detected in a frame of data. A boundary location associated with a detected predetermined number of consecutive control characters from the word aligner unit is identified. The frame of data is aligned in response to the boundary location associated with the detected predetermined number of consecutive control characters.

To enable GNSS (Global Navigation Satellite System) receivers used outdoors to be used also indoors.

A high frequency signal receiving unit receives a first high frequency signal and generates a first intermediate frequency signal. A packet generating unit generates a packet on the basis of the first high frequency signal. A packet output unit outputs the generated packet to a communication path. A packet receiving unit receives the packet via the communication path. A packet interpreting unit performs synchronization processing for the packet and generates a second intermediate frequency signal. A high frequency signal transmitting unit converts the second intermediate frequency signal into a second high frequency signal and transmits the second high frequency signal. A wireless receiver receives the second high frequency signal and performs positioning or time synchronization on the basis of the second high frequency signal.

To enable GNSS (Global Navigation Satellite System) receivers used outdoors to be used also indoors.

A high frequency signal receiving unit receives a first high frequency signal and generates a first intermediate frequency signal. A packet generating unit generates a packet on the basis of the first high frequency signal. A packet output unit outputs the generated packet to a communication path. A packet receiving unit receives the packet via the communication path. A packet interpreting unit performs synchronization processing for the packet and generates a second intermediate frequency signal. A high frequency signal transmitting unit converts the second intermediate frequency signal into a second high frequency signal and transmits the second high frequency signal. A wireless receiver receives the second high frequency signal and performs positioning or time synchronization on the basis of the second high frequency signal.

A system for serializing input data signals and generating an output data signal includes a FIFO memory that launches the input data signals at different phases of a clock signal. The system further includes multiple stages of a serializer circuit, and each stage of the serializer circuit receives a clock signal. Each successive stage includes half the number of serializer circuits that are included in the previous stage, and each successive stage is clocked by a clock signal that transitions at twice the frequency of the previous stage clock signal. The serializer circuits that belong to a single stage receive the clock signal with different phase. The phase and frequency of clock signals of serializer stages are adjusted such that a launched input data signal is outputted as the output data signal. Further, a critical path for each serializer circuit is equal to full clock cycle of the clock signal.