An interface for communicating between two device is provided that includes an interface input for receiving an input signal as well as a comparator circuit coupled to the interface input. The comparator circuit is adapted to provide a clock signal and a data signal based on the input signal to a first memory device having a first input for receiving the data signal and a second input for receiving the clock signal.

A driver circuit for an integrated circuit (IC) is configurable to operate in three different signaling modes, namely, differential signaling mode, single-ended current mode, and single-ended voltage mode. The driver circuit receives first and second input signals from a pre-driver and outputs first and second output signals that conform with the selected one of the three signaling modes.

A transmitter may include a first transmission driver configured to drive a first transmission line according to a first input signal, a second transmission driver configured to drive a second transmission line according to a second input signal, a third transmission driver configured to drive a third transmission line according to a third input signal. The transmitter may further include a first active inductor circuit coupled to an output terminal of the first transmission driver, a second active inductor circuit coupled to an output terminal of the second transmission driver, and a third active inductor circuit coupled to an output terminal of the third transmission driver.

The present disclosure relates to device including first and second terminals connected to a bus, third and fourth terminals connected to power supply and reference potentials. A first transistor and a first resistor are in series between the first terminal and a first diode connected to the third terminal. A second resistor, a second transistor and a second diode are in series between the first and fourth terminals. A third transistor and a third resistor are in series between the first diode and the second terminal. A fourth resistor, a fourth transistor and a third diode are in series between the second and fourth terminals. At each consecutive transmission of a dominant bit and of a recessive bit, a circuit sets the transistors at the ON state during a time period starting with the recessive bit.

A communication node is connected to a transmission line which transmits a differential signal changeable between a high level and a low level and has a high potential signal line and a low potential signal line as a pair of signal lines. The communication node includes: an inter-line potential detector that detects an intermediate potential between the pair of signal lines; a node potential detector that detects an intermediate potential of an operation power source voltage which is supplied to the communication node; and a voltage adjuster that detects a difference between the intermediate potential detected by the inter-line potential detector and the intermediate potential detected by the node potential detector, and adjusts the operation power source voltage in accordance with the difference.

An interface for communicating between two device is provided that includes an interface input for receiving an input signal as well as a comparator circuit coupled to the interface input. The comparator circuit is adapted to provide a clock signal and a data signal based on the input signal to a first memory device having a first input for receiving the data signal and a second input for receiving the clock signal.

A method of manufacturing an electronic device for providing galvanic isolation includes forming a dielectric layer on a semiconductor body and integrating, in the dielectric layer, a galvanic isolation module, the integrating including forming a first metal region at a first height of the dielectric layer. A second metal region is formed at a second height greater than the first height of the dielectric layer, the first and second metal regions being at least one of capacitively and magnetically coupleable together. Forming the second metal region includes etching selective portions of the dielectric layer to form at least one trench having a side wall coupled to a bottom wall through rounded surface portions, and filling each trench with metal material to form the second metal region having rounded edges.

A regenerative differential receiver includes, for example, a transformer arranged to receive a modulated differential signal. A first detector is arranged to source a first output current for indicating a first power level in response to falling voltage of a first line of the modulated differential signal. A second detector is arranged to sink a second output current for indicating a second power level in response to rising voltage of a first line of the modulated differential signal. A cross-coupled latch is arranged to latch a state in response to the first and second power levels. The cross-coupled latch provides, for example, weak non-linear regeneration for increasing receiver gain and maximum operating frequencies.

Certain aspects of the present disclosure relate to methods and apparatus for wireless communication. In certain aspects, the apparatus generally includes a first interface configured to obtain, from a baseband module, a multiplexed signal comprising a control signal, a second interface configured to obtain a power signal, a radio frequency (RF) module, a regulator coupled to the second interface and configured to receive the power signal, and a circuit configured to provide the control signal to the regulator. In certain aspects, the regulator, in response to the control signal, may be configured to generate a supply voltage signal by regulating the power signal and provide the supply voltage signal to the RF module.

A circuit for implementing a differential input receiver is described. The circuit comprises an input circuit having a first input node and a second input node configured to receive a differential input signal; a first output circuit having a first capacitor coupled between the first input node and a first output node and a second capacitor coupled between the second input node and a second output node, wherein the first output circuit generates an output signal at the first output and the second output when the input signal is in a first frequency range; and a second output circuit comprising an amplifier having a first amplifier input coupled to the first input node and a second amplifier input coupled to the second input node, wherein the second output circuit generates an output signal when the input signal is in a second frequency range which extends lower than the first frequency range. A method of implementing a differential input receiver is also described. The circuits and methods also allow for offset compensation.