A transmitter may include a first transmission driver configured to drive a first transmission line according to a first input signal, a second transmission driver configured to drive a second transmission line according to a second input signal, a third transmission driver configured to drive a third transmission line according to a third input signal. The transmitter may further include a first active inductor circuit coupled to an output terminal of the first transmission driver, a second active inductor circuit coupled to an output terminal of the second transmission driver, and a third active inductor circuit coupled to an output terminal of the third transmission driver.

A digital receiver for decoding input data having three states includes a first input coupled to a first data line, a second input coupled to a second data line, a third input coupled to a third data line, and a fourth input coupled to a fourth data line. A first decoder is coupled to a first output, wherein the first decoder is for outputting first data signals in response to the sign of input data on the first data line minus input data on the second line. A second decoder is coupled to a second output, wherein the second decoder is for outputting second data signals in response to the sign of input data on the third data line minus input data on the fourth data line.

An electronic device includes a semiconductor body and a dielectric layer extending over the semiconductor body. A galvanic isolation module includes a first metal region extending in the dielectric layer at a first height and a second metal region extending in the dielectric layer at a second height greater than the first height. The first and second metal regions are capacitively or magnetically coupleable together. The second metal region includes a side wall and a bottom wall coupled to one another through rounded surface portions.

The semiconductor device according to an exemplary embodiment includes: a driver configured to output first and second signals complementary to each other through first and second nodes, respectively; and a receiver detector configured to detect whether a reception circuit of an active state is connected to the first node and the second node according to a voltage of the first node and a voltage of the second node. The receiver detector is configured to compare the voltage of the first node with a first reference voltage, compare the voltage of the second node with a second reference voltage, and detect whether the reception circuit of the active state is connected according to a comparison result of the voltage of the first node and a comparison result of the voltage of the second node.

A line receiver is described. The line receiver may be configured to receive signals transmitted via a communication channel, such as a metal trace on a printed circuit board or a cable. The receiver may comprise a buffer and circuitry for enhancing the trans-conductance gain of the buffer. By enhancing the trans-conductance gain of the buffer, linearity may be improved and susceptibility to process and temperature variations may be limited. Enhancement of the trans-conductance gain may be performed using feedback circuitry coupled to the buffer. The receiver may further comprise mirror circuitry configured to provide a desired current to the load. The receiver may further comprise a gain stage for setting the gain of the receiver to a desired level.

An EHF receiver that determines an initial slicing voltage level and dynamically adjusts the slicing voltage level and/or amplifier gain levels to account for characteristics of the received EHF electromagnetic data signal. The architecture includes an amplifier, detector, adaptive signal slicer, and controller. The detector includes a main detector and replica detector that convert the received EHF electromagnetic data signal into a baseband signal and a reference signal. The controller uses the baseband signal and reference signal to determine an initial slicing voltage level, and dynamically adjust the slicing voltage level and the gain settings of the amplifier to compensate for changing signal conditions.

A digital receiver for decoding input data having three states includes a first input coupled to a first data line, a second input coupled to a second data line, a third input coupled to a third data line, and a fourth input coupled to a fourth data line. A first decoder is coupled to a first output, wherein the first decoder is for outputting first data signals in response to the sign of input data on the first data line minus input data on the second line. A second decoder is coupled to a second output, wherein the second decoder is for outputting second data signals in response to the sign of input data on the third data line minus input data on the fourth data line.

A ringing suppression circuit applicable to a transmitter module in a controller area network is provided, which includes a CANH driver circuit, a CANL driver circuit, a first operable circuit transmitting a CAN high signal, a second operable circuit transmitting a CAN low signal, and a termination component connected between the first operable circuit and the second operable circuit. By sequentially turning on a first, second, and third transistor of the CANH driver circuit and sequentially turning on a fourth, fifth, and sixth transistor of the CANL driver circuit, conventional ringing phenomenon is effectively suppressed. A plurality of transistors may also be configured for implementing the CANH driver circuit or the CANL driver circuit for further reducing a glitch. The transmitter module employing the proposed ringing suppression circuit is able to pull the bus to a recessive state and meanwhile suppress the ringing and improve the maximum data rate.

Scalable telecommunications systems and methods are provided. In one embodiment, a node unit for a scalable telecommunications system comprises: a plurality of universal digital RF transceivers each configured to communicatively couple the node unit to external equipment; one or more universal digital transport interfaces each configured to communicatively couple the node unit to a respective transport link; a universal backplane communicatively coupled to the universal digital RF transceivers and universal digital transport interfaces; and a system controller; wherein each of the universal digital RF transceivers is configured to couple to a respective modular power amplifier and a modular duplexer inserted within the node unit. The system controller is configured to detect capabilities of at least one of the universal digital RF transceivers, the universal digital transport interfaces, the universal backplane, the modular power amplifier and modular duplexer, and adjust parameters of the node unit in response to the detected capabilities.

A driver circuit for driving a transmission line, such as a cable or a metal trace on a printed circuit board is described. The driver may be configured to drive lines with voltages exceeding the maximum voltage than a transistor can withstand for a given fabrication node. The driver may be configured to receive a supply voltage larger than that indicated by manufacturers. The driver may use a fast path and a slow path. Signals provided by the slow path and the fast path may be combine to adapt the input signals to levels that do cause stress to a transistor. A plurality of drivers of the type described herein may be used to provide digital-to-analog conversion.