An object of the present invention is to provide a semiconductor device capable of diagnosing disconnection of a signal line that transmits a command signal in an inspection process even if the command signal is assumed not to be transmitted in the inspection process. A semiconductor device according to the present invention includes a first semiconductor integrated circuit and a control circuit, the control circuit includes a means for controlling a signal line in response to a response signal from the first semiconductor integrated circuit, and the control circuit further includes a means for controlling the signal line regardless of a signal from the first semiconductor integrated circuit.

The present disclosure relates to a secondary device comprising a first port receiving a clock signal from a first port of a primary device and a second port connected to a second port of the primary device. The clock signal determines, for each bit transmission, first, second, third and fourth successive phases. The secondary device puts its second port in a high impedance state during the first, second and fourth phases of each bit transmission. During the third phase of each transmission of a bit of data from the secondary device to the primary device, the secondary device discharges its second port when the transmitted bit has a first value and leaves its second port in a high impedance state when the transmitted bit has a second value.

Decision feedback equalization (DFE) is used to help reduce inter-symbol interference (ISI) from a data signal received via a band-limited (or otherwise non-ideal) channel. A first PAM-4 DFE architecture has low latency from the output of the samplers to the application of the first DFE tap feedback to the input signal. This is accomplished by not decoding the sampler outputs in order to generate the feedback signal for the first DFE tap. Rather, weighted versions of the raw sampler outputs are applied directly to the input signal without further analog or digital processing. Additional PAM-4 DFE architectures use the current symbol in addition to previous symbol(s) to determine the DFE feedback signal. Another architecture transmits PAM-4 signaling using non-uniform pre-emphasis. The non-uniform pre-emphasis allows a speculative DFE receiver to resolve the transmitted PAM-4 signals with fewer comparators/samplers.

Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for correcting transmission errors in multi-wire transition-encoded interface may include determining whether a symbol error is present in the sequence of symbols based on a value of an error detection code (EDC) in the received plurality of bits, generating one or more permutations of the sequence of symbols, where each permutation includes one symbol that is different from corresponding symbols in the sequence of symbols and different from corresponding symbols in other permutations. A permutation in the one or more permutations may be identified as including a corrected sequence of symbols when it produces a decoded EDC value that matches an expected EDC value. The expected EDC value may correspond to a predefined value for EDCs transmitted over the multi-wire interface to enable detection of up to two symbol errors at the receiver.

The present technology relates to a signal processing device, a signal processing method, and a program capable of reducing influence of crosstalk. Provided are: a plurality of comparators; a delay unit adapted to delay output of each of the plurality of comparators; and a subtractor adapted to subtract, from a supplied signal, a signal from the delay unit. The signal processing device processes signals transmitted in N phases and includes (N−1) or more comparators. Each of the plurality of comparators has a different threshold value set and compares a received signal with the threshold value, and in a case where the signal transitions between a plurality of voltage levels, the threshold value is set to a value within adjacent voltage levels. The present technology can be applied to a reception device that receives a signal transmitted in multiple phases and via multiple lines.

Facilitating ad hoc daisy-chaining of dynamically addressable devices having configurable physical layer interfaces together in a serial manner is presented herein. A system can include a group of devices communicatively coupled with respective devices of the group of devices in a daisy-chained manner via physical layer (PHY) interfaces of the respective devices including a group of available communication protocol configurations including a low voltage differential signaling (LVDS) based PHY configuration, a controller area network (CAN) based PHY configuration, and/or a single-ended serial communication PHY configuration including a complementary metal-oxide-semiconductor (CMOS) based interface or a transistor-transistor logic (TTL) based interface. Further, a host device of the system is directly connected, using a single-ended Manchester encoded serial communication interface, to a foremost device of the group of devices and to successive devices of the respective devices, via the foremost device, using the single-ended Manchester encoded serial communication interface.

A device for a serial bus system. The device has a receiver receiving a signal from a bus of the bus system. For a message exchanged between user stations of the bus system, a recessive bus state is overwritable by a dominant bus state and the recessive bus state is generated differently in the first communication phase than in the second communication phase. The receiver generates a digital signal based on the received signal, and the signal being output to a communication control unit for evaluating the data contained in the digital signal. The receiver uses a first and second reception threshold for generating the digital signal in the second communication phase, the second reception threshold having a voltage value lower than that of the first reception threshold or higher than the highest voltage value which, during normal operation, is established on the bus for a dominant bus.

The present invention provides a semiconductor device realizing suppression of increase in consumption power. A semiconductor device has a signal line, a reception buffer circuit which is coupled to an end of the signal line and to which a signal is supplied from the signal line, and a delay element which is wired-OR coupled to an end of the signal line and shapes a waveform of a signal at the end of the signal line.

Devices exchange control signals with each other to ensure proper operation of an overall system. For instance, in a communication system, a baseband processor and a transceiver communicate with each other to exchange information for controlling the respective signal processing parts of the baseband processor and the transceiver. While Serial Peripheral Interfaces (SPIs) can be used, SPI can be extremely slow, and does not provide a protocol for allowing a complex set of control signals to be exchanged between the baseband processor and transceiver. The present disclosure describes a fast control interface which can support various modes of operation in allowing two devices to communicate with each other quickly and effectively.

A LIN receiver includes a single, low power structure for both sleep and silent modes, with a single comparator for detecting LIN signaling during both sleep and silent modes as well as during active mode. In some embodiments, full receiving capability is implemented with a current as low as 5 microamps. In particular, dominant and recessive levels for the wakeup bloc are identical to those of standard LIN levels, fixed at about 3.5 V. Consequently, full LIN receiving capability is available during sleep mode.