An example portable electronic device can include: a first antenna, a second antenna, and a third antenna; a first RFFE, a second RFFE, and a third RFFE which are configured to pre-process an RF signal; a first conductive wiring; a first switch including a (1-1)th terminal connected to the first antenna, a (1-2)th terminal connected to one end of the first conductive wiring, and a (1-3)th terminal connected to the first RFFE; a second switch including a (2-1)th terminal connected to the second antenna, a (2-2)th terminal connected to the third antenna, a (2-3)th terminal connected to the second RFFE, a (2-4)th terminal connected to the third RFFE, and a (2-5)th terminal connected to the other end of the first conductive wiring; an RFIC configured to convert RF signals inputted from the first RFFE, the second RFFE, and the third RFFE into a baseband signal, and convert the baseband signal into an RF signal so as to output the RF signal to the first RFFE; and a communication processor configured to control the first switch so as to sequentially connect the (1-3)th terminal to the (1-1)th terminal and the (1-2)th terminal when the portable electronic device operates in a first transmission mode for transmitting a sounding reference signal (SRS) to the wireless communication network by using the first RFFE, and control the second switch so as to sequentially connect the (2-1)th terminal and the (2-2)th terminal to the (2-5)th terminal while the (1-2)th terminal is connected to the (1-3)th terminal.

An example portable electronic device can include: a first antenna, a second antenna, and a third antenna; a first RFFE, a second RFFE, and a third RFFE which are configured to pre-process an RF signal; a first conductive wiring; a first switch including a (1-1)th terminal connected to the first antenna, a (1-2)th terminal connected to one end of the first conductive wiring, and a (1-3)th terminal connected to the first RFFE; a second switch including a (2-1)th terminal connected to the second antenna, a (2-2)th terminal connected to the third antenna, a (2-3)th terminal connected to the second RFFE, a (2-4)th terminal connected to the third RFFE, and a (2-5)th terminal connected to the other end of the first conductive wiring; an RFIC configured to convert RF signals inputted from the first RFFE, the second RFFE, and the third RFFE into a baseband signal, and convert the baseband signal into an RF signal so as to output the RF signal to the first RFFE; and a communication processor configured to control the first switch so as to sequentially connect the (1-3)th terminal to the (1-1)th terminal and the (1-2)th terminal when the portable electronic device operates in a first transmission mode for transmitting a sounding reference signal (SRS) to the wireless communication network by using the first RFFE, and control the second switch so as to sequentially connect the (2-1)th terminal and the (2-2)th terminal to the (2-5)th terminal while the (1-2)th terminal is connected to the (1-3)th terminal.

Providing a reception device and a communication system capable of preventing signal quality degradation and improving signal transmission efficiency in a case where a data signal is transmitted via a transmission line that connects a plurality of transmission devices and a reception device. Provided is a reception device including a compensation circuit and an adjustment circuit. The compensation circuit is connected to a transmission line connected to each of the plurality of transmission devices and compensates a signal transmitted from each of the transmission devices in time division. The adjustment circuit adjusts operation of the compensation circuit, in which the adjustment circuit adjusts the operation of the compensation circuit by using a first adjustment value that adjusts the operation of the compensation circuit and is read from a recording medium storing the first adjustment value.

A receiving device determines that a first PHY needs to be added to a first FlexE group in a working state. The receiving device performs a deskew on the first PHY or each PHY in the first FlexE group based on a received data stream corresponding to the first PHY and a received data stream corresponding to each PHY in the first FlexE group, and restores a data stream corresponding to a client from a PHY in the first FlexE group. If a skew between the data stream corresponding to the first PHY and the data stream corresponding to each PHY in the first FlexE group after the deskew is performed is zero, the receiving device restores a data stream corresponding to a client from a PHY in a second FlexE group so that flexibility of adjusting a PHY in a FlexE group in a working state is improved.

A serial communication apparatus capable of efficiently eliminating a timing lag between serial data transferred via a plurality of routes in serial communication is provided. The serial communication apparatus transfers serial data transmitted from a transmitting side communication unit disposed on a transmitting side to a receiving side communication unit disposed on a receiving side via a plurality of lanes. The transmitting side communication unit comprises a packet transmitting unit configured to divide transmission data into equal parts according to the number of the lanes, distribute the divided transmission data to each lane as a data main body, and add header information indicating the type of the transmission data to the divided transmission data distributed to each lane. The receiving side communication unit comprises a received packet skew adjusting unit configured to adjust skew of data received in each lane. The received packet skew adjusting unit detects the header information of the data received in each lane, writes the data main body of the received data to a data buffer at a detection timing, and starts data transfer from the data buffer to the outside at a timing when a writing access of the data main body of a predetermined number of cycles is completed in each lane.

Disclosed are high-speed data transmitting/receiving system and method capable of removing simultaneous switching noise and ISI at low cost and a small area. A transmitter used in the data transmitting/receiving system includes: a data mapping unit which maps 2-bit input data to one of codes, wherein the voltage level of a first signal line, the voltage level of a second signal line, and the voltage level of a third signal line are set in each of the codes; and a transmit driver which outputs data corresponding to the input data through the first signal line, the second signal line, and the third signal line having the voltage levels corresponding to the mapped code. Here, each of the voltage levels is ‘+1’, ‘0’ or ‘−1’, and the number of signal lines having the voltage level of ‘+1’ is the same as the number of signal lines having the voltage level of ‘−1’.

A multi-tap Differential Feedforward Equalizer (DFFE) configuration with both precursor and postcursor taps is provided. The DFFE has reduced noise and/or crosstalk characteristics when compared to a Feedforward Equalizer (FFE) since DFFE uses decision outputs of slicers as inputs to a finite impulse response (FIR) unlike FFE which uses actual analog signal inputs. The digital outputs of the tentative decision slicers are multiplied with tap coefficients to reduce noise. Further, since digital outputs are used as the multiplier inputs, the multipliers effectively work as adders which are less complex to implement. The decisions at the outputs of the tentative decision slicers are tentative and are used in a FIR filter to equalize the signal; the equalized signal may be provided as input to the next stage slicers. The bit-error-rate (BER) of the final stage decisions are lower or better than the BER of the previous stage tentative decisions.

A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.

A high-speed data receiver includes interleaver circuitry configured to divide a received data stream into a plurality of interleaved paths for processing, spectral content detection circuitry configured to derive spectral content information from data on each of the plurality of interleaved paths, sorting circuitry configured to bin the derived spectral content information according to energy levels, stream attribute determination circuitry configured to determine, based on sorted spectral content, one or more of path offsets of the interleaved paths, gain mismatch among interleaved paths, signal bandwidth mismatch and pulse width mismatch, and equalization circuitry configured to correct the one or more of the determined offsets, the determined gain mismatch and the determined signal width mismatch. Equalization circuitry may be configured to equalize a gain-normalized signal by separately adjusting respective bandwidth actuators of each respective interleaved path and respective pulse width actuators of each respective interleaved path.

A multi-lane transmitting apparatus includes lanes, and each lane includes a serializer circuit to convert parallel bits to serial bits. A clock signal generator generates a first clock signal having phases. A deserializer circuit converts serial bits to parallel bits. A Built-In Self-Test (BIST) circuit includes a signal generator circuit for generating a signal having bits in a defined pattern. A comparator circuit compares a pattern of bits of an output signal with the defined pattern. A BIST lane circuit monitors a status of the lanes. A BIST central circuit receives the status and determines if a number of lanes having an unmatched status is less than a threshold value. A phase extrapolator circuit adjusts a phase of the first clock signal when the number of the lanes is less than the threshold value.