A device includes a receiver analog front-end circuit including a path shared by an internal loopback current path and a calibration current path, wherein the receiver analog front-end circuit is configured to perform an internal test using the internal loopback current path while in a test mode, and equalize a first data signal while in a normal mode, the equalizing the first data signal including removing an offset from the first data signal using the calibration current path.

A de-skew circuit, a de-skew method and a receiver are provided. The de-skew circuit includes N data synchronization circuits and a controller. An nth data synchronization circuit among the N data synchronization circuits includes an nth command detector and an nth buffer. The nth command detector changes an nth command detection signal when an nth input data stream satisfies a single channel condition. The nth buffer stores the nth input data stream in response to a voltage change of the nth command detection signal. The controller receives the nth command detection signal and changes a pop signal when a global channel condition is satisfied. The nth buffer outputs an nth timing-aligned data stream in response to a voltage change of the pop signal.

A de-skew circuit, a de-skew method and a receiver are provided. The de-skew circuit includes N data synchronization circuits and a controller. An nth data synchronization circuit among the N data synchronization circuits includes an nth command detector and an nth buffer. The nth command detector changes an nth command detection signal when an nth input data stream satisfies a single channel condition. The nth buffer stores the nth input data stream in response to a voltage change of the nth command detection signal. The controller receives the nth command detection signal and changes a pop signal when a global channel condition is satisfied. The nth buffer outputs an nth timing-aligned data stream in response to a voltage change of the pop signal.

Methods and systems are described for receiving symbols of a codeword via wires of a multi-wire bus, the codeword representing an aggregate sum of a plurality of sub-channel constituent codewords, each sub-channel constituent codeword representing a weight applied to an associated sub-channel vector of a plurality of sub-channel vectors of an orthogonal matrix, generating a plurality of comparator outputs using a plurality of common-mode resistant multi-input comparators (MICs), each common-mode resistant MIC having a set of input coefficients representing a corresponding sub-channel vector of the plurality of sub-channel vectors, each sub-channel vector (i) mutually orthogonal and (ii) orthogonal to a common-mode sub-channel vector, outputting a set of forward-channel output bits formed based on the plurality of comparator outputs, obtaining a sequence of reverse-channel bits, and transmitting the sequence of reverse-channel bits by sequentially transmitting common-mode codewords over the wires of the multi-wire bus.

A first physical layer coding data block flow and a second physical layer coding data block flow are received. A first data flow is obtained according to the first physical layer coding data block flow and the second physical layer coding data block flow. Multiple subframe headers are generated. A second data flow is obtained according to the first data flow and the multiple subframe headers. Data blocks in the second data flow are distributed to a first physical medium dependent (PMD) sublayer circuit and to a second PMD sublayer circuit to obtain a first PMD sublayer data flow and a second PMD sublayer data flow.

A first physical layer coding data block flow and a second physical layer coding data block flow are received. A first data flow is obtained according to the first physical layer coding data block flow and the second physical layer coding data block flow. Multiple subframe headers are generated. A second data flow is obtained according to the first data flow and the multiple subframe headers. Data blocks in the second data flow are distributed to a first physical medium dependent (PMD) sublayer circuit and to a second PMD sublayer circuit to obtain a first PMD sublayer data flow and a second PMD sublayer data flow.

A particular overall architecture for transmission over a bonded channel system consisting of two interconnected MoCA (Multimedia over Coax Alliance) 2.0 SoCs (Systems on a Chip) and a method and apparatus for the case of a “bonded” channel network. With a bonded channel network, the data is divided into two segments, the first of which is transported over a primary channel and the second of which is transported over a secondary channel.

A particular overall architecture for transmission over a bonded channel system consisting of two interconnected MoCA (Multimedia over Coax Alliance) 2.0 SoCs (Systems on a Chip) and a method and apparatus for the case of a “bonded” channel network. With a bonded channel network, the data is divided into two segments, the first of which is transported over a primary channel and the second of which is transported over a secondary channel.

A signal processing device includes an interface, which includes a demodulation processing unit that executes demodulation processing, a processing unit that executes demux processing or the like, and a sync signal line, a valid signal line, a clock signal line, and a data signal line disposed between the demodulation processing unit and the processing unit, that transmits data signals as two-bit parallel transmission.

A method of handling signal transmission applicable to a display system includes a plurality of steps. The steps include transmitting a reset signal embedded in a first data signal to each of at least one source driver via a first data channel, generating a first control signal for setting the at least one source driver, and transmitting the first control signal embedded in a second data signal to each of the at least one source driver via a second data channel when the reset signal is transmitted via the first data channel.