According to one embodiment, an interface system includes a receiver, a first clock generator, a second clock generator, and a sampling circuit. The receiver is configured to receive a first clock and serial data from a host. The first clock generator includes a first voltage controlled oscillator (VCO) and is configured to generate a second clock on the basis of the first clock. The second clock generator includes a second voltage controlled oscillator (VCO) and is configured to generate a third clock on the basis of the serial data. The sampling circuit is configured to sample reception data on the basis of the third clock and the serial data.

A system includes a first device and a second device coupled to a link having one or more lanes. The first device is to transmit two or more frames to synchronize the one or more data lanes, where each frame comprises a quantity of bits. The second device is to receive a first set of bits from each data lane corresponding to the quantity of bits in each frame of the two or more frames. The second device is to determine that the first set of bits received from a data lane of the one or more data lanes does not correspond to a frame boundary of the two or more frames. The second device is further to synchronize each data lane of the one or more data lanes with respect to the frame boundary, responsive to determining that the first set of bits does not correspond to the frame boundary.

A wireless communication protocol which operates with multi-link devices (MLDs) having simultaneous transmit and receive (STR) link pairs to allow transmitting a long MU PPDU by an originator on a first link, which is acknowledged (Ack) by a recipient on a second link. The Ack on the second link may be on a single resource unit (RU) which may be shared by multiple stations. The Ack may be received during the MP PPDU on the first link, making it a quick Ack. In many cases this allows the originator to perform a retransmission within the same PPDU, thus especially benefitting real-time traffic which is latency sensitive.

A network device distributes a plurality of symbol blocks, received via a plurality of input streams, to a plurality of output links comprised in a defined connection according to a mapping of the symbol blocks to the output links. Responsive to an input stream of the plurality of input streams being empty such that an expected symbol block is not received, the network device distributes idle data to the output link mapped to the expected symbol block to maintain the mapping of the symbol blocks to the output links. The network device transmits the symbol blocks and idle data over the defined connection via the plurality of output links and according to the distribution.

A network device distributes a plurality of symbol blocks, received via a plurality of input streams, to a plurality of output links comprised in a defined connection according to a mapping of the symbol blocks to the output links. Responsive to an input stream of the plurality of input streams being empty such that an expected symbol block is not received, the network device distributes idle data to the output link mapped to the expected symbol block to maintain the mapping of the symbol blocks to the output links. The network device transmits the symbol blocks and idle data over the defined connection via the plurality of output links and according to the distribution.

An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herein called the “ISI Ratio” are described which permit higher communications speed, lower system power consumption, and reduced implementation complexity.

An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herein called the “ISI Ratio” are described which permit higher communications speed, lower system power consumption, and reduced implementation complexity.

Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for correcting transmission errors in multi-wire transition-encoded interface may include determining whether a symbol error is present in the sequence of symbols based on a value of an error detection code (EDC) in the received plurality of bits, generating one or more permutations of the sequence of symbols, where each permutation includes one symbol that is different from corresponding symbols in the sequence of symbols and different from corresponding symbols in other permutations. A permutation in the one or more permutations may be identified as including a corrected sequence of symbols when it produces a decoded EDC value that matches an expected EDC value. The expected EDC value may correspond to a predefined value for EDCs transmitted over the multi-wire interface to enable detection of up to two symbol errors at the receiver.

Apparatus, systems and methods for error detection in transmissions on a multi-wire interface are disclosed. A method for correcting transmission errors in multi-wire transition-encoded interface may include determining whether a symbol error is present in the sequence of symbols based on a value of an error detection code (EDC) in the received plurality of bits, generating one or more permutations of the sequence of symbols, where each permutation includes one symbol that is different from corresponding symbols in the sequence of symbols and different from corresponding symbols in other permutations. A permutation in the one or more permutations may be identified as including a corrected sequence of symbols when it produces a decoded EDC value that matches an expected EDC value. The expected EDC value may correspond to a predefined value for EDCs transmitted over the multi-wire interface to enable detection of up to two symbol errors at the receiver.

This application is directed to transferring data over a data link coupled between two electronic devices. The data link includes a retimer having a full data path and a bit level data path that are coupled in parallel. The data link is initiated with the full data path and a first sequence of data packets is transferred via the full data path in accordance with a low data rate setting. While transferring the first sequence of data packets, the first sequence of data packets is manipulated in the full data path to establish a connection of the data link, and in response to establishing the connection of the data link, the data link is switched from the full data path to the bit level data path.