A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.

A system and method for synchronizing two devices in communication with each other. When communication between the two devices is to be established, a synchronization process may be invoked. In an embodiment, a first device may initiate sending synchronization signals having rising edge and falling edge pairs. The second device may include a controller configured to receive the synchronization signals. However, noise may inhibit the ability of the controller to correctly receive and/or interpret the synchronization signals. Noise may cause detection components to falsely detect noise as a synchronization signal or may cause detection components to miss detection of an actual synchronization signal. A window generator may be used to generate comparison windows for the controller to detect synchronization signals. Further, the detection window duration and start times may be adjusted based on previously detected (or undetected) synchronization signals in order to compensate for noise overshadowing synchronization signals.

Methods and systems are described for generating, with a local oscillator and an adjustable phase interpolator, a data-sampling clock and a variable-phase-offset eye-measurement clock, forming a received data signal using a multi-input comparator, generating, using a data slicer and the data sampling clock, a receive sample of the received data signal, and generating, using at least one eye slicer and the variable-phase-offset eye-measurement clock, a plurality of eye characteristic measurements by adjusting a sampling threshold of the at least one eye slicer and a phase offset of the variable-phase-offset eye-measurement clock.

Methods and systems are described for receiving, at a data-driven phase comparator circuit, a plurality of data signals in parallel and one or more phases of a local oscillator signal, the data-driven phase comparator circuit comprising a plurality of partial phase comparators, generating a plurality of partial phase-error signals using the partial phase comparators, each partial phase-error signal generated by receiving (i) a corresponding phase of the local oscillator signal and (ii) a corresponding data signal of the plurality of data signals and responsive to a determination that a transition occurred in the corresponding data signal, generating the partial phase-error signal based on a comparison of the corresponding phase of the local oscillator signal and the corresponding data signal, and generating a composite phase-error signal by summing the plurality of partial phase error signals for setting a local oscillator in a lock condition.

Methods and systems are described for receiving, at a data-driven phase comparator circuit, a plurality of data signals in parallel and one or more phases of a local oscillator signal, the data-driven phase comparator circuit comprising a plurality of partial phase comparators, generating a plurality of partial phase-error signals using the partial phase comparators, each partial phase-error signal generated by receiving (i) a corresponding phase of the local oscillator signal and (ii) a corresponding data signal of the plurality of data signals and responsive to a determination that a transition occurred in the corresponding data signal, generating the partial phase-error signal based on a comparison of the corresponding phase of the local oscillator signal and the corresponding data signal, and generating a composite phase-error signal by summing the plurality of partial phase error signals for setting a local oscillator in a lock condition.

A programmable delay line comprises a delay stage responsive to an analog control signal and responsive to one or more digital control signals. The delay stage generates an output signal that is delayed relative to an input signal by a delay amount. The delay amount controlled by a value of the analog control signal and one or more values of the digital control signals. A method for controlling a delay locked loop circuit comprises providing, to a programmable delay line of the delay locked loop circuit, a one or more digital signals, and providing, to the programmable delay line, an analog signal. A first portion of a delay produced by the programmable delay line corresponds to values of the one or more digital signals. A second portion of the delay produced by the programmable delay line corresponds to a value of the analog signal.

A signal detection method associated with a constellation diagram corresponding to a modulation scheme is provided for enhancing the reliability of code rate search. A mask is provided between two adjacent constellation points in the modulation scheme. The signal detection method includes: receiving a plurality of signals, and mapping the plurality of signals to the constellation diagram; when a first signal among the plurality of signals is located in the mask, discarding the first signal; and when a second signal among the plurality of signals outside located in the mask, determining a constellation point corresponding to the second signal.

A signal detection method associated with a constellation diagram corresponding to a modulation scheme is provided for enhancing the reliability of code rate search. A mask is provided between two adjacent constellation points in the modulation scheme. The signal detection method includes: receiving a plurality of signals, and mapping the plurality of signals to the constellation diagram; when a first signal among the plurality of signals is located in the mask, discarding the first signal; and when a second signal among the plurality of signals outside located in the mask, determining a constellation point corresponding to the second signal.

A baseband IC for performing digital communication with an RFIC and a device including the same. The baseband IC for performing digital communication with an RFIC includes a digital interface circuit configured to receive a frame signal including at least one sampled signal from the RFIC according to a digital interface protocol, reconstruct the at least one sampled signal from the frame signal, and transfer the reconstructed sampled signal to a baseband modem in synchronization with a reception reference signal, and a sample synchronization manager configured to generate the reception reference signal, wherein the frame signal is transmitted from the RFIC to the baseband IC in synchronization with a transmission reference signal.

A baseband IC for performing digital communication with an RFIC and a device including the same. The baseband IC for performing digital communication with an RFIC includes a digital interface circuit configured to receive a frame signal including at least one sampled signal from the RFIC according to a digital interface protocol, reconstruct the at least one sampled signal from the frame signal, and transfer the reconstructed sampled signal to a baseband modem in synchronization with a reception reference signal, and a sample synchronization manager configured to generate the reception reference signal, wherein the frame signal is transmitted from the RFIC to the baseband IC in synchronization with a transmission reference signal.