Aspects of the disclosure provide a wireless node in a wireless network with a grid topology for routing a message. The wireless node includes circuitry configured to receive a message including a destination node identification number, calculate a destination column and a destination row based on the destination node identification number, determine a next hop address based on the destination column and the destination row, and transmit the message including the next hop address to a next hop node.

A method of operating a hypercube network of processing devices includes determining that a plurality of the processing devices are storing data to be processed at a single processing device, obtaining the addresses of the plurality of processing devices storing the data to be processed, determining the most common number for each digit of the addresses of the plurality of processing devices storing the data to be processed, generating a new address comprising the determined most common number for each digit, and transferring the data to be processed to the processing device with the generated new address.

An IPv6 packet processing method and apparatus where a first routing device obtains an IPv6 packet, and sends the IPv6 packet to a next-hop routing device. The IPv6 packet includes an IPv6 extension header that includes preceding general indication information, where the preceding general indication information includes first information, and where the first information is used to indicate to process the IPv6 packet only on a data plane of a routing device and not to send the IPv6 packet to a CPU.

An apparatus includes an interface and a processor. The interface communicates with a network including network elements interconnected in a Cartesian topology. The processor defines first and second groups of turns, each turn includes a hop from a previous network element to a current network element and a hop from the current network element to a next network element. Based on the turns, the processor specifies rules that when applied to packets traversing respective network elements, guarantee that no deadlock conditions occur in the network. The rules for a given network element include (i) forwarding rules to reach a given target without traversing the turns of the second group, and (ii) Virtual Lane (VL) modification rules for reassigning packets, which traverse turns of the first group and which are assigned to a first VL, to a different second VL. The processor configures the given network element with the rules.

In accordance with one or more preferred implementations, an overlay network in the form of a dispersive virtual network is implemented utilizing data deflects to implement and facilitate routing in a data plane and call processing deflects to implement and facilitate routing in a control plane. Various nodes in the dispersive virtual network, such as end devices running dispersive virtual networking client software, establish communication channels to these deflects running dispersive virtual networking protocols transported by user datagram protocol (UDP) frames, transmission control protocol (TCP) streams, and hypertext transfer protocol (HTTP) streams. In accordance with one or more preferred implementations, software allows nodes in a dispersive virtual network to automatically detect the channel types that are available at the time the node must initiate a new session, and automatically configure the most efficient communication channel without requiring input from an end user or from a network administrator.

An apparatus includes a network interface and a processor. The network interface communicates with a network including switches interconnected in a Cartesian topology having multiple dimensions. The processor predefines turn types of turns in the Cartesian topology, each turn traverses first and second hops along first and second dimensions having same or different respective identities, and each turn type is defined at least by identities of the first and second dimensions. The processor searches for a preferred route from a source switch to a destination switch, by evaluating candidate routes based on the number of VLs required for preventing a deadlock condition caused by the candidate route. The number of VLs required depends on a sequential pattern of turn types formed by the candidate route. The processor configures one or more switches in the network to route packets from the source switch to the destination switch along the preferred route.

An apparatus includes an interface and a processor. The interface communicates with a network including network elements interconnected in a Cartesian topology. The processor defines first and second groups of turns, each turn includes a hop from a previous network element to a current network element and a hop from the current network element to a next network element. Based on the turns, the processor specifies rules that when applied to packets traversing respective network elements, guarantee that no deadlock conditions occur in the network. The rules for a given network element include (i) forwarding rules to reach a given target without traversing the turns of the second group, and (ii) Virtual Lane (VL) modification rules for reassigning packets, which traverse turns of the first group and which are assigned to a first VL, to a different second VL. The processor configures the given network element with the rules.

Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. The programmable coarse-grain routing network and smart memory circuitry may be implemented on an active interposer die. the smart memory circuitry may be configured to perform higher level functions than simple read and write operations. The smart memory circuitry may carry out command based low cycle count operations using a state machine without requiring execution of a program code, complex microcontroller based multicycle operations, and other non-generic microcontroller based smart RAM functions.

Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. The programmable coarse-grain routing network and smart memory circuitry may be implemented on an active interposer die. the smart memory circuitry may be configured to perform higher level functions than simple read and write operations. The smart memory circuitry may carry out command based low cycle count operations using a state machine without requiring execution of a program code, complex microcontroller based multicycle operations, and other non-generic microcontroller based smart RAM functions.

Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for three-dimensionally stacked neural network accelerators. In one aspect, a method includes obtaining data specifying that a tile from a plurality of tiles in a three-dimensionally stacked neural network accelerator is a faulty tile. The three-dimensionally stacked neural network accelerator includes a plurality of neural network dies, each neural network die including a respective plurality of tiles, each tile has input and output connections. The three-dimensionally stacked neural network accelerator is configured to process inputs by routing the input through each of the plurality of tiles according to a dataflow configuration and modifying the dataflow configuration to route an output of a tile before the faulty tile in the dataflow configuration to an input connection of a tile that is positioned above or below the faulty tile on a different neural network die than the faulty tile.