Patent classifications
H04L47/56
APPARATUS, METHOD AND COMPUTER PROGRAM
An apparatus (113) comprising means for performing: receiving one or more forwarding tables from a centralized network configuration entity (101) of a time sensitive network, wherein the forwarding tables comprise entry information; and determining, based at least in part on the one or more forwarding tables, rules for mapping at least one uplink data stream of the time sensitive network to at least one of: a protocol data unit session (135, 137) and a quality of service flow (129, 131, 133).
APPARATUS, METHOD AND COMPUTER PROGRAM
An apparatus (113) comprising means for performing: receiving one or more forwarding tables from a centralized network configuration entity (101) of a time sensitive network, wherein the forwarding tables comprise entry information; and determining, based at least in part on the one or more forwarding tables, rules for mapping at least one uplink data stream of the time sensitive network to at least one of: a protocol data unit session (135, 137) and a quality of service flow (129, 131, 133).
PACKET BUFFERING METHOD, INTEGRATED CIRCUIT SYSTEM, AND STORAGE MEDIUM
This application relates to the field of data communication, and in particular, to a packet buffering method, an integrated circuit system, and a storage medium. The method can improve utilization of the on-chip buffer. The packet buffering method may be applied to a network device. The network device includes a first storage medium and a second storage medium. The first storage medium is a local buffer, and the second storage medium is an external buffer. The method may include: receiving a first packet, and identifying a queue number of the first packet, where the queue number indicates a queue for storing the first packet; querying a queue latency based on the queue number; determining a first latency threshold based on usage of the first storage medium; and buffering the first packet in the first storage medium or the second storage medium based on the queue latency and the first latency threshold.
PACKET BUFFERING METHOD, INTEGRATED CIRCUIT SYSTEM, AND STORAGE MEDIUM
This application relates to the field of data communication, and in particular, to a packet buffering method, an integrated circuit system, and a storage medium. The method can improve utilization of the on-chip buffer. The packet buffering method may be applied to a network device. The network device includes a first storage medium and a second storage medium. The first storage medium is a local buffer, and the second storage medium is an external buffer. The method may include: receiving a first packet, and identifying a queue number of the first packet, where the queue number indicates a queue for storing the first packet; querying a queue latency based on the queue number; determining a first latency threshold based on usage of the first storage medium; and buffering the first packet in the first storage medium or the second storage medium based on the queue latency and the first latency threshold.
Time sensitive networking device
The present disclosure generally relates to a device, method, or system for time sensitive networking. In an example, the device can include a time-sensitive networking controller and a scheduler. The device also includes an enhanced gate control list maintained on the time-sensitive networking controller to include a direct memory access address, a launch time, and a pre-fetch time for a data packet. The device may also include a transmitter of the time-sensitive networking controller to transmit the data packet retrieved using the direct memory access address at the launch time identified by the scheduler.
Asynchronous medium access control layer scheduler for directional networks
An asynchronous medium access control layer scheduler increases efficiency for directional mesh networks by removing extra overhead in the time slots. The efficiency is increased by dividing time slots into sub-slots to allow for a receiving node to be offset by at least one sub-slot from the transmitting node. This enables the scheduler to more efficiently schedule operations for the nodes so that nodes can be performing other functions rather than waiting to receive a transmission or waiting after transmitting a transmission. The sub-slots may be sized to approximate the transmission propagation time or time of flight delay.
Asynchronous medium access control layer scheduler for directional networks
An asynchronous medium access control layer scheduler increases efficiency for directional mesh networks by removing extra overhead in the time slots. The efficiency is increased by dividing time slots into sub-slots to allow for a receiving node to be offset by at least one sub-slot from the transmitting node. This enables the scheduler to more efficiently schedule operations for the nodes so that nodes can be performing other functions rather than waiting to receive a transmission or waiting after transmitting a transmission. The sub-slots may be sized to approximate the transmission propagation time or time of flight delay.
Queueing system with head-of-line block avoidance
Control logic circuitry stores packets in a queue in an order in which the packets are received. A head entry of the queue corresponds to an oldest packet in the order. The control logic circuitry receives flow control information corresponding to multiple target devices including at least a first target device and a second target device. The control logic circuitry determines, using the flow control information, whether the oldest packet stored in the head entry can be transferred to the first target device, and in response to determining that the oldest packet stored in the head entry cannot be transferred to the first target device, i) selects an other entry with an other packet behind the head entry according to the order, and ii) transfers the other packet to the second target device prior to transferring the oldest packet in the head entry to the first target device.
Queueing system with head-of-line block avoidance
Control logic circuitry stores packets in a queue in an order in which the packets are received. A head entry of the queue corresponds to an oldest packet in the order. The control logic circuitry receives flow control information corresponding to multiple target devices including at least a first target device and a second target device. The control logic circuitry determines, using the flow control information, whether the oldest packet stored in the head entry can be transferred to the first target device, and in response to determining that the oldest packet stored in the head entry cannot be transferred to the first target device, i) selects an other entry with an other packet behind the head entry according to the order, and ii) transfers the other packet to the second target device prior to transferring the oldest packet in the head entry to the first target device.
Method and apparatus for determining packet dequeue rate
A method for determining a packet dequeue rate includes allocating a plurality of consecutive blocks in a first memory to a first packet, storing the first packet and a first length in the plurality of blocks, where the first length is of a first packet queue and is obtained when the first packet is enqueued into the first packet queue, and determining, based on a first span and the first length stored, a first rate at which a packet in the first packet queue is dequeued, where the first span is equal to a difference between a second time and a first time, the first time is when the first packet is enqueued into the first packet queue, and the second time is when the first packet is dequeued from the first packet queue.