Systems and techniques for network on a chip based computer architectures and distributing data without shared pointers therein are described. A described system includes computing resources; and a memory resource configured to maintain a dedicated memory region of the memory resource for distributed read operations requested by the computing resources. The computing resources can generate a packet to fetch data from the dedicated memory region without using memory addresses of respective data elements. The memory resource can receive the first packet, determine whether the first packet indicates the distributed read operation, and determine that the dedicated memory region is non-empty. Further, the memory resource can fetch one or more data elements from the dedicated memory region based on the first packet indicating the distributed read operation and the dedicated memory region being non-empty, and send a packet that includes the one or more fetched data elements.

Disclosed herein are methods and apparatuses for processing network traffic by a queuing system which may include: receiving pointers to chunks of memory allocated responsive to receipt of network traffic, the chunks of memory each including a portion of a queue batch, wherein the queue batch includes a plurality of queue requests; generating a data structure including the pointers and a reference count; assigning the queue request to a second core; generating a first structured message for the first queue request; and storing the first structured message in a structured message passing queue associated with the second core, wherein a second processing thread associated with the second core, responsive to receiving the structured message, processes the first queue request by retrieving the first queue request from at least one of the chunks of memory.

A packet forwarding apparatus includes a first storage device and a processor. The first storage device has a plurality of buffers allocated therein, and at least one buffer included in the plurality of buffers is arranged to buffer at least one packet. The processor is arranged to execute a Linux kernel to perform software-based packet forwarding associated with the at least one packet. The at least one buffer allocated in the first storage device is recycled through direct memory access (DMA) management, and is reused for buffering at least one other packet.

A network interface card with traffic shaping capabilities and methods of network traffic shaping with a network interface card are provided. The network interface card and method can shape traffic originating from one or more applications executing on a host network device. The applications can execute in a virtual machine or containerized computing environment. The network interface card and method can perform or include several traffic shaping mechanisms including, for example and without limitation, a delayed completion mechanism, a time-indexed data structure, a packet builder, and a memory manager.

In one embodiment, a computer system includes a payload sub-system including interfaces to connect with respective devices, transfer data with the respective devices, and receive write transactions from the respective devices, a classifier to classify the received write transactions into payload data and control data, and a payload cache to store the classified payload data, and a processing unit (PU) sub-system including a local PU cache to store the classified control data, wherein the payload cache and the local PU cache are different physical caches in respective different physical locations in the computer system, and processing core circuitry configured to execute software program instructions to perform control and packet processing responsively to the control data stored in the local PU cache.

In one embodiment, a computer system includes a payload sub-system including interfaces to connect with respective devices, transfer data with the respective devices, and receive write transactions from the respective devices, a classifier to classify the received write transactions into payload data and control data, and a payload cache to store the classified payload data, and a processing unit (PU) sub-system including a local PU cache to store the classified control data, wherein the payload cache and the local PU cache are different physical caches in respective different physical locations in the computer system, and processing core circuitry configured to execute software program instructions to perform control and packet processing responsively to the control data stored in the local PU cache.

Described are programmable IO devices configured to perform operations. These operations comprise: determining a set of range-based elements for a network; sorting the set of range-based elements according to a global order among the range-based elements; generating an interval table from the sorted range-based elements; generating an interval binary search tree from the interval table; propagating data stored in subtrees of interior stages of the interval binary search tree to subtrees of a last stage of the interval binary search tree such that the interior stages do not comprise data; converting the interval binary search tree to a Pensando Tree; compressing multiple levels of the Pensando Tree into cache-lines; and assembling the cache-lines in the memory unit such that each stage can compute an address of a next-cache line to be fetched by a next stage.

Described are programmable IO devices configured to perform operations. These operations comprise: determining a set of range-based elements for a network; sorting the set of range-based elements according to a global order among the range-based elements; generating an interval table from the sorted range-based elements; generating an interval binary search tree from the interval table; propagating data stored in subtrees of interior stages of the interval binary search tree to subtrees of a last stage of the interval binary search tree such that the interior stages do not comprise data; converting the interval binary search tree to a Pensando Tree; compressing multiple levels of the Pensando Tree into cache-lines; and assembling the cache-lines in the memory unit such that each stage can compute an address of a next-cache line to be fetched by a next stage.

Data requests can be serviced by multiple paths of smart network interface cards (NICs). For example, a system can receive a request for data at a first path of a smart NIC. The first path can be a hardware-implemented path. The system can send one or more parameters of the request to a second path of the smart NIC. The second path can be a slower path than the first path and configured to execute a routing algorithm for the request. The system can receive routing information for the request from the second path based on the routing algorithm and transmit the request to a storage node based on the routing information.

Data requests can be serviced by multiple paths of smart network interface cards (NICs). For example, a system can receive a request for data at a first path of a smart NIC. The first path can be a hardware-implemented path. The system can send one or more parameters of the request to a second path of the smart NIC. The second path can be a slower path than the first path and configured to execute a routing algorithm for the request. The system can receive routing information for the request from the second path based on the routing algorithm and transmit the request to a storage node based on the routing information.