A method involves transferring a transmittal data block from a transmitting device via an Ethernet connection to a receiving device which has a storage for storing a transferred transmittal data block, and a processor for at least partially processing the transferred transmittal data block stored in the storage. The transmitting device forms from the data of the transmittal data block a sequence of Ethernet packets, comprising respectively management data and a transmittal data sub-block. The receiving device receives the Ethernet packets of the respective sequence and, while employing at least a part of the management data, writes the transmittal data sub-blocks of the received Ethernet packets of the sequence of Ethernet packets for the transmittal data block to the storage, wherein not upon or after the writing each of the transmittal data sub-blocks an interrupt is sent to the processor.

A method involves transferring a transmittal data block from a transmitting device via an Ethernet connection to a receiving device which has a storage for storing a transferred transmittal data block, and a processor for at least partially processing the transferred transmittal data block stored in the storage. The transmitting device forms from the data of the transmittal data block a sequence of Ethernet packets, comprising respectively management data and a transmittal data sub-block. The receiving device receives the Ethernet packets of the respective sequence and, while employing at least a part of the management data, writes the transmittal data sub-blocks of the received Ethernet packets of the sequence of Ethernet packets for the transmittal data block to the storage, wherein not upon or after the writing each of the transmittal data sub-blocks an interrupt is sent to the processor.

Logic may store at least a portion of an incoming packet at a memory location in a host device in response to a communication from the host device. Logic may compare the incoming packet to a digest in an entry of a primary array. When the incoming packet matches the digest, logic may retrieve a full entry from the secondary array and compare the full entry with the first incoming packet. When the full entry matches the first incoming packet, logic may store at least a portion of the first incoming packet at the memory location. And, in the absence of a match between the first incoming packet and the digest or full entry, logic may compare the first incoming packet to subsequent entries in the primary array to identify a full entry in the secondary array that matches the first incoming packet.

Logic may store at least a portion of an incoming packet at a memory location in a host device in response to a communication from the host device. Logic may compare the incoming packet to a digest in an entry of a primary array. When the incoming packet matches the digest, logic may retrieve a full entry from the secondary array and compare the full entry with the first incoming packet. When the full entry matches the first incoming packet, logic may store at least a portion of the first incoming packet at the memory location. And, in the absence of a match between the first incoming packet and the digest or full entry, logic may compare the first incoming packet to subsequent entries in the primary array to identify a full entry in the secondary array that matches the first incoming packet.

A circuit with a first buffer, a second buffer, a third buffer, a fourth buffer, a first data input for first data, a second data input for second data, a data output, and control logic is disclosed. The control logic connects the first data input to one of the buffers, connects the second data input to one of the buffers, and connects the data output to one of the buffers, swap the buffer currently connected to the first data input for a non-connected buffer when first data have been validly written through the first data input into the buffer currently connected to the first data input, swap the buffer currently connected to the second data input for the non-connected buffer when second data have been validly written through the second data input into the buffer currently connected to the second data input.

A circuit with a first buffer, a second buffer, a third buffer, a fourth buffer, a first data input for first data, a second data input for second data, a data output, and control logic is disclosed. The control logic connects the first data input to one of the buffers, connects the second data input to one of the buffers, and connects the data output to one of the buffers, swap the buffer currently connected to the first data input for a non-connected buffer when first data have been validly written through the first data input into the buffer currently connected to the first data input, swap the buffer currently connected to the second data input for the non-connected buffer when second data have been validly written through the second data input into the buffer currently connected to the second data input.

Aspects of the present disclosure provide techniques for compressing data packets for cellular internet of things (CIoT) communications. An example method generally includes establishing at least one prefill buffer common to one or more UEs, wherein the prefill buffer includes a plurality of common strings, generating a compressed packet by finding matches to the common strings in at least one of a header portion or payload portion of the packet and associating identifiers with the common strings, and transmitting the packet.

This invention concerns the transmitting and receiving of digital media packets, such as audio and video channels and lighting instructions. In particular, the invention concerns the transmitting and receiving of redundant media packet streams. Samples are extracted from a first and second media packet stream. The extracted samples are written to a buffer based on the output time of each sample. Extracted samples having the same output time are written to the same location in the buffer. Both media packet streams are simply processed all the way to the buffer without any particular knowledge that one of the packet streams is actually redundant. This simplifies the management of the redundant packet streams, such as eliminating the need for a “fail-over” switch and the concept of an “active stream”, The location is the storage space allocated to store one sample. The extracted sample written to the location may be written over another extracted sample from a different packet stream previously written to the location. These extracted samples written to the same location may be identical.

This invention concerns the transmitting and receiving of digital media packets, such as audio and video channels and lighting instructions. In particular, the invention concerns the transmitting and receiving of redundant media packet streams. Samples are extracted from a first and second media packet stream. The extracted samples are written to a buffer based on the output time of each sample. Extracted samples having the same output time are written to the same location in the buffer. Both media packet streams are simply processed all the way to the buffer without any particular knowledge that one of the packet streams is actually redundant. This simplifies the management of the redundant packet streams, such as eliminating the need for a “fail-over” switch and the concept of an “active stream”, The location is the storage space allocated to store one sample. The extracted sample written to the location may be written over another extracted sample from a different packet stream previously written to the location. These extracted samples written to the same location may be identical.

Reassembly of member cells into a packet comprises receiving an incoming member cell of a packet from a switching fabric wherein each member cell comprises a segment of the packet and a header, generating a reassembly key using selected information from the incoming member cell header wherein the selected information is the same for all member cells of the packet, checking a reassembly table in a content addressable memory to find an entry that includes a logic key matching the reassembly key, and using a content index in the found entry and a sequence number of the incoming member cell within the packet, to determine a location offset in a reassembly buffer area for storing the incoming member cell at said location offset in the reassembly buffer area for the packet for reassembly.