Systems, methods, and computer-readable media are disclosed for an apparatus coupled to a communication bus, where the apparatus includes a queue and a controller to manage operations of the queue. The queue includes a first space to store a first information for a first traffic type, with a first flow class, and for a first virtual channel of communication between a first communicating entity and a second communicating entity. The queue further includes a second space to store a second information for a second traffic type, with a second flow class, and for a second virtual channel of communication between a third communicating entity and a fourth communicating entity. The first traffic type is different from the second traffic type, the first flow class is different from the second flow class, or the first virtual channel is different from the second virtual channel. Other embodiments may be described and/or claimed.

Techniques for performing shared queue management utilizing shuffle sharding are described. For an event, one shared queue can be selected by first identifying a shard of a pool of queues, selecting two or more queues from the shard, and selecting the one queue that has a minimum queue load from those queues in the selected two or more queues. The selection significantly reduces or eliminates negative impacts upon a user or user function from activity of other users that utilize the shared queues.

Methods and apparatus for active queue management in user space networking stacks. Unlike prior art monolithic networking stacks, the exemplary networking stack architecture described hereinafter includes various components that span multiple domains (both in-kernel, and non-kernel). For example, unlike traditional “socket” based communication, disclosed embodiments can transfer data directly between the kernel and user space domains. Additionally, user space networking stacks require a new flow control methodology that is responsive to networking congestion and/or packet loss. For example, embodiments of the present disclosure introduce a flow advisory table that may, for example, utilize an eventing methodology for active queue management in addition to, or alternatively then, legacy active queue management. Exemplary systems can support multiple networking protocol stack instances (including an in-kernel traditional network stack) as well as flow advisory tables (and legacy active queue management).

A network interface controller (NIC) capable of efficient memory access is provided. The NIC can be equipped with an operation logic block, a signaling logic block, and a tracking logic block. The operation logic block can maintain an operation group associated with packets requesting an operation on a memory segment of a host device of the NIC. The signaling logic block can determine whether a packet associated with the operation group has arrived at or departed from the NIC. Furthermore, the tracking logic block can determine that a request for releasing the memory segment has been issued. The tracking logic block can then determine whether at least one packet associated with the operation group is under processing in the NIC. If no packet associated with the operation group is under processing in the NIC, tracking logic block can notify the host device that the memory segment can be released.

A network interface controller (NIC) capable of efficient memory access is provided. The NIC can be equipped with an operation logic block, a signaling logic block, and a tracking logic block. The operation logic block can maintain an operation group associated with packets requesting an operation on a memory segment of a host device of the NIC. The signaling logic block can determine whether a packet associated with the operation group has arrived at or departed from the NIC. Furthermore, the tracking logic block can determine that a request for releasing the memory segment has been issued. The tracking logic block can then determine whether at least one packet associated with the operation group is under processing in the NIC. If no packet associated with the operation group is under processing in the NIC, tracking logic block can notify the host device that the memory segment can be released.

Examples described herein relate to a network interface device. In some examples, the network interface device includes a host interface; a direct memory access (DMA) circuitry; a network interface; and circuitry. The circuitry can be configured to: based on received telemetry data from at least one switch: select a next hop network interface device from among multiple network interface devices based on received telemetry data. In some examples, the telemetry data is based on congestion information of a first queue associated with a first traffic class, the telemetry data is based on per-network interface device hop-level congestion states from at least one network interface device, the first queue shares bandwidth of an egress port with a second queue, the first traffic class is associated with packet traffic subject to congestion control based on utilization of the first queue, and the utilization of the first queue is based on a drain rate of the first queue and a transmit rate from the egress port.

Examples described herein relate to a network interface device. In some examples, the network interface device includes a host interface; a direct memory access (DMA) circuitry; a network interface; and circuitry. The circuitry can be configured to: based on received telemetry data from at least one switch: select a next hop network interface device from among multiple network interface devices based on received telemetry data. In some examples, the telemetry data is based on congestion information of a first queue associated with a first traffic class, the telemetry data is based on per-network interface device hop-level congestion states from at least one network interface device, the first queue shares bandwidth of an egress port with a second queue, the first traffic class is associated with packet traffic subject to congestion control based on utilization of the first queue, and the utilization of the first queue is based on a drain rate of the first queue and a transmit rate from the egress port.

An apparatus for switching network traffic includes an ingress packet forwarding engine and an egress packet forwarding engine. The ingress packet forwarding engine is configured to determine, in response to receiving a network packet, an egress packet forwarding engine for outputting the network packet and enqueue the network packet in a virtual output queue. The egress packet forwarding engine is configured to output, in response to a first scheduling event and to the ingress packet forwarding engine, information indicating the network packet in the virtual output queue and that the network packet is to be enqueued at an output queue for an output port of the egress packet forwarding engine. The ingress packet forwarding engine is further configured to dequeue, in response to receiving the information, the network packet from the virtual output queue and enqueue the network packet to the output queue.

Methods, systems, and computer programs are presented for processing Ethernet packets at a Field Programmable Gate Array (FPGA). One programmable integrated circuit includes: an internal network on chip (iNOC) comprising rows and columns, clusters, coupled to the iNOC, comprising a network access point (NAP) and programmable logic; and an Ethernet controller coupled to the iNOC. When the controller operates in packet mode, each complete inbound Ethernet packet is sent from the controller to one of the NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller. The controller is configurable to operate in quad segment interface (QSI) mode where each complete inbound Ethernet packet is broken into segments, which are sent from the controller to different NAPs via the iNOC, where two or more NAPs are configurable to receive the complete inbound Ethernet packets from the controller.

A switch architecture enables ports to stash packets in unused buffers on other ports, exploiting excess internal bandwidth that may exist, for example, in a tiled switch. This architecture leverages unused port buffer memory to improve features such as congestion handling and error recovery.