Provided is a collision prevention system of a multi-master including: a plurality of external modules; and an integrated device. The integrated device includes: a plurality of interfaces connected respectively to the plurality of external modules and respectively controlled by corresponding external modules; a plurality of internal modules; a plurality of dedicated buffers connected respectively to the plurality of interfaces and the plurality of internal modules; and a common block connected to the plurality of dedicated buffers and controlled by the plurality of interfaces and the plurality of internal modules. The plurality of dedicated buffers includes a GBU and a plurality of LBUs. The GBU and the plurality of LBUs are connected to two neighboring GBUs and a plurality of LBUs to form a ring communication topology, which transmits ring communication data in one direction. The common block is connected to the ring communication topology through the GBU.

A packet processing method includes: a first device receives a packet from a second device; the first device determines a first queue buffer used to store the packet, and determines a first upper limit value of the first queue buffer based on an available value of a first port buffer and an available value of a global buffer, where the global buffer includes at least one port buffer, the first port buffer is one of the at least one port buffer, the first port buffer includes at least one queue buffer, and the first queue buffer is one of the at least one queue buffer. The first device processes the packet based on the first upper limit value of the first queue buffer, an occupation value of the first queue buffer, and a size of the packet.

Embodiments herein describe a group of APs that uses a shared radar cache to select a new channel after vacating a current channel when performing dynamic frequency selection (DFS). The group of APs can set aside memory to store status information about the DFS channels in the frequency band. For example, when one AP detects a radar event (and has to vacate a DFS channel), the AP updates an entry for that channel in the shared radar cache. The APs can also query the cache to determine a new channel after vacating its current channel. That is, the shared radar cache may store the most recent radar events occurring in a channel. In this manner, the APs can select a new channel that has little or no recent radar events, which reduces the likelihood the AP will have to vacate the new channel.

A packet filtering system uses linked zero-based binary search trees to filter received packets. The binary search trees may be generated from filter conditions defining filter parameters for filtering packets.

A 5G communication system or pre-5G communication system for supporting a higher data rate than that of a beyond 4G communication system such as an LTE is provided. A method by an apparatus for controlling buffers in a wireless communication system comprises storing information related to a packet in at least one of a first buffer or a second buffer, transmitting data generated based on the packet, and, when an acknowledgement signal is received for the data, discarding the information.

A method for data transmission may be implemented on an electronic device having one or more processors. The one or more processors may include a master queue including a master queue head and a plurality of primary ports that are connected to each other using a serial link. The method may include operating the master queue head to obtain a message. The method may also include operating the master queue head to segment the message into a plurality of segments. The method may also include operating the master queue head to transmit the plurality of segments to a first primary port of the plurality of primary ports in the master queue. The method may also include operating the first primary port to transmit the plurality of segments to a second primary port of the plurality of primary ports in the master queue.

A regular buffer and a shadow buffer are maintained at a receiver host. Responsive to receiving a data flow from a sender host that is clock-synchronized with the receiver host using a common reference clock, a first indication of data of the data flow is stored to the regular buffer, the shadow buffer is transitioned from an idle state to an active state, and a counter of the shadow buffer is incremented that indicates a unit of data traffic received. A dynamic drain rate is determined based on a number of units of the data removed from the regular buffer per unit of time while the shadow buffer is in the active state, where the shadow buffer reverts to an idle state responsive to a break in the receiver host receiving the data flow. Dwell time is calculated as a function of the counter of the shadow buffer and the dynamic drain rate, and a congestion signal for the data flow is determined based on the dwell time.

A regular buffer and a shadow buffer are maintained at a receiver host. Responsive to receiving a data flow from a sender host that is clock-synchronized with the receiver host using a common reference clock, a first indication of data of the data flow is stored to the regular buffer, the shadow buffer is transitioned from an idle state to an active state, and a counter of the shadow buffer is incremented that indicates a unit of data traffic received. A dynamic drain rate is determined based on a number of units of the data removed from the regular buffer per unit of time while the shadow buffer is in the active state, where the shadow buffer reverts to an idle state responsive to a break in the receiver host receiving the data flow. Dwell time is calculated as a function of the counter of the shadow buffer and the dynamic drain rate, and a congestion signal for the data flow is determined based on the dwell time.

A circuit with a first buffer, a second buffer, a third buffer, a fourth buffer, a first data input for first data, a second data input for second data, a data output, and control logic is disclosed. The control logic connects the first data input to one of the buffers, connects the second data input to one of the buffers, and connects the data output to one of the buffers, swap the buffer currently connected to the first data input for a non-connected buffer when first data have been validly written through the first data input into the buffer currently connected to the first data input, swap the buffer currently connected to the second data input for the non-connected buffer when second data have been validly written through the second data input into the buffer currently connected to the second data input.

A network interface controller (NIC) capable of on-demand paging is provided. The NIC can be equipped with a host interface, an operation logic block, and an address logic block. The host interface can couple the NIC to a host device. The operation logic block can obtain from a remote device, a request for an operation based on a virtual memory address. The address logic block can obtain, from the operation logic block, a request for an address translation for the virtual memory address and issue an address translation request to the host device via the host interface. If the address translation is unsuccessful, the address logic block can send a page request to a processor of the host device via the host interface. The address logic block can then determine that a page has been allocated in response to the page request and reissue the address translation request.