A network interface controller (NIC) capable of performing message passing interface (MPI) list matching is provided. The NIC can include a host interface, a network interface, and a hardware list-processing engine (LPE). The host interface can couple the NIC to a host device. The network interface can couple the NIC to a network. During operation, the LPE can receive a match request and perform MPI list matching based on the received match request.

A network interface controller (NIC) capable of performing message passing interface (MPI) list matching is provided. The NIC can include a host interface, a network interface, and a hardware list-processing engine (LPE). The host interface can couple the NIC to a host device. The network interface can couple the NIC to a network. During operation, the LPE can receive a match request and perform MPI list matching based on the received match request.

A buffer shortage management system includes a first networking device with ports included in a buffer pool. A second networking device forwards a first data flow to the first networking device through LAG port(s) in the buffer pool. The first networking device determines that a total buffer pool utilization has reached a threshold that effects a first data flow received through a non-LAG port on the first networking device. The first networking device then identifies that the first data flow and third data flow(s) are received through the LAG port(s), determines that the first data flow has a higher utilization of the buffer pool than the third data flow(s) and, in response, transmits a first buffer shortage notification to the second networking device that causes the second networking device to modify its forwarding parameters to redirect the first data flow from the first networking device to a third networking device.

Systems and devices can include a controller and a command queue to buffer incoming write requests into the device. The controller can receive, from a client across a link, a non-posted write request (e.g., a deferred memory write (DMWr) request) in a transaction layer packet (TLP) to the command queue; determine that the command queue can accept the DMWr request; identify, from the TLP, a successful completion (SC) message that indicates that the DMWr request was accepted into the command queue; and transmit, to the client across the link, the SC message that indicates that the DMWr request was accepted into the command queue. The controller can receive a second DMWr request in a second TLP; determine that the command queue is full; and transmit a memory request retry status (MRS) message to be transmitted to the client in response to the command queue being full.

A memory device is configured as single chip to achieve routing control, bandwidth control, traffic monitoring, buffering, and access control of network functions. The memory device includes a search unit that includes a first memory unit and performs a search operation by searching, from the first memory unit, a piece of data corresponding to an input search key, a statistical information processing unit that includes a second memory unit that stores statistical information including the input search key, with which the piece of data has been successfully searched by the search unit, and an address of the piece of data in the first memory unit, and an arithmetic operation unit that updates the statistical information when the search unit successfully searches the pieces of data corresponding to the input search key.

Efficient garbage collection techniques for network packets and other units of data are described. Constituent portions of a data unit are stored in buffer entries spread out across multiple distinct banks. Linking data is generated and stored on a per-bank basis. The linking data defines, for each bank in which data for the data unit is stored, a chain of all entries in that bank that store data for the data unit. When the data unit is dropped or otherwise disposed of, a chain's head entry address may be placed in a garbage collection list for the corresponding bank. A garbage collector uses the linking data to gradually follow the chain of entries for the given bank, and frees each entry in the chain along the way. Optionally, certain addresses in the chain, including each chain's tail address, are immediately freed for the corresponding bank, without waiting to follow the chain.

Systems and methods are provided for passing data amongst a plurality of switches having a plurality of links attached between the plurality of switches. At a switch, a plurality of load signals are received from a plurality of neighboring switches. Each of the plurality of load signals are made up of a set of values indicative of a load at each of the plurality of neighboring switches providing the load signal. Each value within the set of values provides an indication for each link of the plurality of links attached thereto as to whether the link is busy or quiet. Based upon the plurality of load signals, an output link for routing a received packet is selected, and the received packet is routed via the selected output link.

Systems and methods are provided for passing data amongst a plurality of switches having a plurality of links attached between the plurality of switches. At a switch, a plurality of load signals are received from a plurality of neighboring switches. Each of the plurality of load signals are made up of a set of values indicative of a load at each of the plurality of neighboring switches providing the load signal. Each value within the set of values provides an indication for each link of the plurality of links attached thereto as to whether the link is busy or quiet. Based upon the plurality of load signals, an output link for routing a received packet is selected, and the received packet is routed via the selected output link.

One embodiment provides a network interface controller (NIC). The NIC can include a storage device, a network interface, a hardware list-processing engine (LPE), and a message state table (MST) logic block. The storage device can store an MST. The network interface can couple the NIC to a network. The LPE can perform message matching on a first packet of a message received via the network interface. The MST logic block can store results of the message matching in the MST and receive a request to read the results of the message matching from the MST if the NIC receives a second packet associated with the message.

One embodiment provides a network interface controller (NIC). The NIC can include a storage device, a network interface, a hardware list-processing engine (LPE), and a message state table (MST) logic block. The storage device can store an MST. The network interface can couple the NIC to a network. The LPE can perform message matching on a first packet of a message received via the network interface. The MST logic block can store results of the message matching in the MST and receive a request to read the results of the message matching from the MST if the NIC receives a second packet associated with the message.