Examples herein are directed to communicating on a communication bus in accordance with a message-based signal protocol. One or more messages are generated with a data field, in which a portion of the data field is reserved for a signature. The signature has a bit length corresponding to a bit length of the reserved portion of the data field. The signature is coded in the portion of the data field reserved for the signature, and at least one message is transmitted with the signature coded therein. Each message received on the communication bus and having a signature coded in a data field therein is authenticated based on the signature, and processed by removing the signature from the data field and decoding the message with the signature removed.

A cryptographic method includes providing memory locations for storing encrypted data. The memory locations have respective addresses and are accessible via a communication bus. The method includes receiving over the communication bus access requests to the memory locations, wherein the access requests include burst requests for access to respective sets of the memory locations starting from respective start addresses, and calculating as a function of the start addresses encryption/decryption cryptographic masks based on cryptographic keys. Plain text data is received for encryption and the method includes applying the cryptographic masks to the plain text data to obtain therefrom encrypted data, and including the encrypted data into output data for transmission over the communication bus.

A mechanism is described for facilitating unified accelerator for classical and post-quantum digital signature schemes in computing environments. A method includes unifying classical cryptography and post-quantum cryptography through a unified hardware accelerator hosted by a trusted platform of the computing device. The method may further include facilitating unification of a first finite state machine associated with the classical cryptography and a second finite state machine associated with the post-quantum cryptography though one or more of a single the hash engine, a set of register file banks, and a modular exponentiation engine.

An integrated security device, including: an encryption/decoding processing unit for executing processing necessary for authentication by using a logic circuit that forms an encryption/decoding function; a selector for selecting signals whose number corresponds to a specific number of lines from among signals from a plurality of intermediate nodes of the logic circuit in accordance with a selection signal; and a signal processing unit having a function of detecting a glitch caused by the signals corresponding to the specific number of lines, for implementing both a function of generating a physical random number and a function of generating a device identifier by a physical characteristic based on the glitch detected by switch-selecting the signals corresponding to the specific number of lines.

A processor includes a plurality of registers, an instruction decoder to receive an instruction to process a KECCAK state cube of data representing a KECCAK state of a KECCAK hash algorithm, to partition the KECCAK state cube into a plurality of subcubes, and to store the subcubes in the plurality of registers, respectively, and an execution unit coupled to the instruction decoder to perform the KECCAK hash algorithm on the plurality of subcubes respectively stored in the plurality of registers in a vector manner.

The invention is, firstly, a cryptographic apparatus for encrypting unencrypted data, comprising an input module for inputting the unencrypted data and an output module for outputting encrypted data, and a key automaton (44) adapted for converting the unencrypted data into the encrypted data, and the key automaton (44) is an composition of automata said composition of automata having a set of states and a set of input signals identical to each other and being implemented as a permutation automaton without output signals, said composition of automata comprises at least one factor automaton without output signals, each of the unencrypted data and the encrypted data has a character set identical to each other, and the set of states and the set of input signals, respectively, consist of blocks obtained from all possible combinations of said character set, wherein the blocks are of a predetermined block length. The invention is, furthermore, a cryptographic apparatus for decrypting encrypted data. The invention is, thirdly, a cryptographic method for encrypting unencrypted data. The invention is, fourthly, a cryptographic method for decrypting encrypted data.

A quantum resistant smart card is configured to enable access to mobile or integrated telecommunications networks for a cellular communication device, and comprises: encryption means configured for an encryption of data by a standard of at least 256-bit encryption from the list comprising at least AES-256 as defined in the ISO/IEC 18033-3:2011 standard and eAES; dynamic loading means configured to dynamically load in an intended legacy communication device an upgraded protocol stack enabling the intended legacy communication device to connect to a New Radio network by reusing existing frequencies mastered by the intended legacy communication device; and at least one hardware accelerator system which enables the smart card to provide support for the encryption of data according to the standard of at least 256-bit encryption from the list comprising at least AES-256 as defined in the ISO/IEC 18033-3:2011 standard and eAES.

A device is suggested for processing input data including a hardware accelerator generating a first hash value based on a first portion of the input data and a second hash value based on a second portion of the input data, wherein the first hash value is generated based on a first configuration of the hardware accelerator and wherein the second hash value is generated based on a second configuration of the hardware accelerator. Also, a method for operating such device is provided.

Disclosed herein is an apparatus for calculating a cryptographic component R.sup.2 mod n for a cryptographic function, where n is a modulo number and R is a constant greater than n. The apparatus comprises a processor configured to set a start value to be equal to R mod n, perform b iterations of a shift and subtract operation on the start value to produce a base value, wherein the start value is set to be equal to the base value after each iteration, set a multiplication operand to be equal to the base value, and perform k iterations of a Montgomery modular multiplication of the multiplication operand with the multiplication operand to produce an intermediate result, wherein the multiplication operand is set to be equal to the intermediate result after each iteration, wherein the shift and subtract operation comprises determining a shifted start value which is equivalent to the start value multiplied by two, and subtracting n from the shifted start value if the shifted start value is greater than or equal to n.

Disclosed herein is an apparatus for calculating a cryptographic component R.sup.2 mod n for a cryptographic function, where n is a modulo number and R is a constant greater than n. The apparatus comprises an arithmetic logic unit configured to iteratively perform Montgomery multiplication of a first operand with a second operand to produce an intermediate result, wherein the first operand and the second operand are set to the intermediate result after each iteration, responsive to a termination condition being met, determine an adjustment parameter indicative of a difference between the intermediate result and the cryptographic component, and perform Montgomery multiplication of the intermediate result with the adjustment parameter, to calculate the cryptographic component for the cryptographic function.