A solid-state imaging device including: a pixel array unit in which a plurality of pixels outputting an analog pixel signal are arranged in a two-dimensional matrix form; a ramp signal generation unit configured to generate and output a ramp wave; a clock generation unit configured to generate and output multiphase clocks; and a signal-processing unit, wherein the signal-processing unit including: a plurality of analog-to-digital conversion circuits, and a plurality of repeater circuits, wherein each of the plurality of analog-to-digital conversion circuits includes: a comparison unit, and a latch unit, wherein each of the plurality of the analog-to-digital conversion circuits outputs the digital value according to the state of the phase held by each latch circuit, and wherein each of the plurality of the repeater circuits corresponding to the same set are arranged side by side, and the repeater circuits are connected in series.

An optical sensor includes: a semiconductor layer including a first region, a second region, and a third region between the first region and the second region; a gate electrode facing to the semiconductor layer; a gate insulating layer between the third region and the gate electrode, the gate insulating layer including a photoelectric conversion layer: a signal detection circuit including a first signal detection transistor, a first input of the first signal detection transistor being electrically connected to the first region; a first transfer transistor connected between the first region and the first input; and a first capacitor having one end electrically connected to the first input. The signal detection circuit detects an electrical signal corresponding to a change of a dielectric constant of the photoelectric conversion layer, the change being caused by incident light.

An imaging system includes a plurality of pixel circuits each having a photodiode, a biasing circuit and a charge-to-voltage converter. The photodiode is configured to generate charges in response to light or radiation. The biasing circuit is configured to provide a constant bias voltage across the photodiode so as to drain the charges generated by the photodiode. The charge-to-voltage converter is configured to accumulate the charges drained by the biasing circuit and convert the accumulated charges into a corresponding output voltage.

The image sensor includes a pixel array including a plurality of unit pixels each including a single transistor and a photodiode connected to a body of the single transistor, a row driver block configured to enable one of a plurality of rows in the pixel array to enter a readout mode, and a readout block configured to sense and amplify a pixel signal output from each of a plurality of unit pixels included in the row that has entered the readout mode.

An imager integrated circuit intended to cooperate with an optical system configured to direct light rays from a scene to an inlet face of the circuit, the circuit being configured to perform a simultaneous stereoscopic capture of N images corresponding to N distinct views of the scene, each of the N images corresponding to light rays directed by a portion of the optical system which is different from those directing the rays corresponding to the N−1 other images, including: N subsets of pixels made on a same substrate, each of the N subsets of pixels being intended to perform the capture of one of the N associated images, means interposed between each of the N subsets of pixels and the inlet face of the circuit, and configured to pass the rays corresponding to the image associated with said subset of pixels and block the other rays.

In order to improve imaging performance, an imaging apparatus is provided to include an image capturing unit configured to detect incident light and generate a raw image data, a compression unit configured to compress the raw image data to generate a coded data having a data amount smaller than that of the raw image data, and an output unit configured to output the coded data to a processing unit for processing the coded data. Furthermore, the image capturing unit, the compression unit, and the output unit are configured to be within a same semiconductor package.

An image sensor system with an image sensor that generates a first image and a second image. The first and second images are transmitted to a processor in a time overlapping manner. By way of example, the images may be transferred to the processor in an interleaving manner or provided on separate dedicated busses.

A first flip-flop outputs a first output signal as a first switch signal that controls a first switch. A second flip-flop outputs a second output signal based on a clock signal and the first output signal. A first inverting circuit generates a first inverted signal obtained by inverting the first output signal. A second AND circuit outputs a signal that is an AND of the first inverted signal and the second output signal, as a second switch signal that controls a second switch.

A first flip-flop outputs a first output signal as a first switch signal that controls a first switch. A second flip-flop outputs a second output signal based on a clock signal and the first output signal. A first inverting circuit generates a first inverted signal obtained by inverting the first output signal. A second AND circuit outputs a signal that is an AND of the first inverted signal and the second output signal, as a second switch signal that controls a second switch.

An apparatus is described. The apparatus includes a program controller to fetch and issue instructions. The apparatus includes an execution lane having at least one execution unit to execute the instructions. The execution lane is part of an execution lane array that is coupled to a two dimensional shift register array structure, wherein, execution lane s of the execution lane array are located at respective array locations and are coupled to dedicated registers at same respective array locations in the two-dimensional shift register array.