Patent classifications
H04N25/67
IMAGE SENSOR WITH ACTIVE CAPACITANCE CANCELLATION CIRCUITRY TO REDUCE PIXEL OUTPUT SETTLING TIME
An image sensor may include an array of image pixels arranged in rows and columns. Each column of pixels may be coupled to current source transistors and capacitance cancellation circuitry. The capacitance cancellation circuitry may include capacitors, a common source amplifier transistor, an autozero switch, a switch for selectively deactivating at least one of the capacitors during sample-and-hold reset and sample-and-hold signal operations.
IMAGE SENSOR WITH ACTIVE CAPACITANCE CANCELLATION CIRCUITRY TO REDUCE PIXEL OUTPUT SETTLING TIME
An image sensor may include an array of image pixels arranged in rows and columns. Each column of pixels may be coupled to current source transistors and capacitance cancellation circuitry. The capacitance cancellation circuitry may include capacitors, a common source amplifier transistor, an autozero switch, a switch for selectively deactivating at least one of the capacitors during sample-and-hold reset and sample-and-hold signal operations.
Solid-state image pickup apparatus, correction method, and electronic apparatus
The present disclosure relates to a solid-state image pickup apparatus, a correction method, and an electronic apparatus, enabled to suppress an apparent uncomfortable feeling of an image output from a solid-state image pickup apparatus in which pixels of different OCL shapes are mounted mixedly. A solid-state image pickup apparatus according to an aspect of the present disclosure includes a pixel array in which a first pixel in which an OCL (On Chip Lens) of a standard size is formed and a second pixel in which an OCL of a size different from the standard size is formed are present mixedly, and a correction section that corrects a pixel value of the first pixel that is positioned in the vicinity of the second pixel among the first pixels on the pixel array. The present disclosure can be applied to, for example, a CMOS image sensor.
Solid-state image pickup apparatus, correction method, and electronic apparatus
The present disclosure relates to a solid-state image pickup apparatus, a correction method, and an electronic apparatus, enabled to suppress an apparent uncomfortable feeling of an image output from a solid-state image pickup apparatus in which pixels of different OCL shapes are mounted mixedly. A solid-state image pickup apparatus according to an aspect of the present disclosure includes a pixel array in which a first pixel in which an OCL (On Chip Lens) of a standard size is formed and a second pixel in which an OCL of a size different from the standard size is formed are present mixedly, and a correction section that corrects a pixel value of the first pixel that is positioned in the vicinity of the second pixel among the first pixels on the pixel array. The present disclosure can be applied to, for example, a CMOS image sensor.
UNDER-DISPLAY CAMERA SYSTEMS AND METHODS
An example image capture device includes a display configured to display captured images, a camera sensor, the camera sensor being disposed to receive light through at least a portion of the display, memory configured to store captured images, and one or more processors coupled to the camera sensor, the display, and the memory. The one or more processors are configured to receive a signal from a sensor. The one or more processors are configured to determine, based at least in part on the signal, a user interface mode. The user interface mode includes a first mode having a first number of black pixels or a second mode having a second number of black pixels. The first number is greater than the second number. The one or more processors are also configured to receive image data from the camera sensor.
Per-pixel detector bias control
A pixel includes a photo-diode, an integration capacitor arranged to receive a photo current from the photo-diode and to store charge developed from the photo current; and an injection transistor disposed between the photo-diode and the integration capacitor that controls flow of the photo current from the photo-diode to the integration capacitor, the injection transistor having a gate, a source electrically coupled to the photo-diode at a first node, and a drain electrically coupled to the integration capacitor. The injection transistor is a silicon-oxide-nitride-oxide-silicon (SONOS) FET having its gate set to a SONOS gate voltage to control a detector bias voltage of the photo-diode at the first node.
Adaptive image processing
An imaging device includes one or more processors; and a computer readable medium storing instructions that, when executed by the one or more processors, cause the imaging device to perform functions including: capturing a first image and thereafter a second image; making a determination of whether or not a difference between the first image and the second image is greater than a threshold value; generating a third image by processing the second image using an image processing algorithm that corresponds to the determination; and displaying the third image.
Adaptive image processing
An imaging device includes one or more processors; and a computer readable medium storing instructions that, when executed by the one or more processors, cause the imaging device to perform functions including: capturing a first image and thereafter a second image; making a determination of whether or not a difference between the first image and the second image is greater than a threshold value; generating a third image by processing the second image using an image processing algorithm that corresponds to the determination; and displaying the third image.
A/D converter including comparison circuit and image sensor including same
An A/D converter and an image sensor are disclosed. The image sensor includes: a pixel array including a plurality of pixels; a ramp signal generator configured to generate a ramp signal; and a comparison circuit configured to output a comparison result signal by comparing a pixel signal output by the pixel array with the ramp signal. The comparison circuit includes: a first comparator stage configured to output a first stage output signal according to a result of comparing the pixel signal with the ramp signal, to a first circuit node; a limiter including an n-type transistor having one end connected to the first circuit node and an opposite end to which power supply voltage is applied; and a second comparator stage configured to generate the comparison result signal by shaping the first stage output signal.
SYSTEMS AND METHODS FOR CALIBRATING, CORRECTING AND PROCESSING IMAGES ON A RADIOGRAPHIC DETECTOR
A radiographic imaging system includes a radiographic detector programmed to display the patient identifying information in human readable form and to access information about the patient stored in locations accessible through a network. Embodiments of methods and/or apparatus for a radiographic imaging system can include a radiographic detector including an image receptor to receive incident radiation and generate uncorrected electronic image data; network accessible storage and/or processor to generate calibration-corrected image data from the uncorrected electronic image data provided from the detector. The calibration-corrected image data can be further processed by the network accessible processor before transmitting a corrected image (e.g., DICOM image) back to the radiographic imaging system.