A solid-state imaging element according to the present disclosure includes a photoelectric conversion layer, a first insulating layer (101), and a second insulating layer (102). The photoelectric conversion layer (photoelectric conversion film PD) includes an insulating film (GFa), a charge storage layer (203), and a photoelectric conversion film (PD) stacked between a first electrode (201) and a second electrode (202). The first insulating layer (101) is provided with gates of some pixel transistors in which the charge storage layer serves as a source, a drain, and a channel in a plurality of pixel transistors that processes signal charges photoelectrically converted by the photoelectric conversion film (PD). The second insulating layer (102) is provided with a pixel transistor other than the some pixel transistors in the plurality of pixel transistors.

A semiconductor device according to the present disclosure includes: a first charge accumulation unit capable of accumulating a charge; a first initialization unit that is connected to the first charge accumulation unit and initializes the first charge accumulation unit; and a first voltage switching unit that is connected to the first initialization unit and is capable of selectively supplying a first voltage and a second voltage different from the first voltage to the first initialization unit.

The dynamic range of a solid-state imaging element including a comparator is expanded.

The solid-state imaging element includes a pixel circuit and a comparison transistor. In the solid-state imaging element, the pixel circuit generates a pixel signal and outputs the pixel signal to a vertical signal line. Further, the comparison transistor has a source connected to a constant current source configured to supply a constant current to the vertical signal line. The comparison transistor has a gate to which a predetermined reference signal is input. Further, the comparison transistor has a drain from which a comparison result between the pixel signal and the reference signal is output.

In one example, an apparatus comprises: a first sensor layer, including an array of pixel cells configured to generate pixel data; and one or more semiconductor layers located beneath the first sensor layer with the one or more semiconductor layers being electrically connected to the first sensor layer via interconnects. The one or more semiconductor layers comprises on-chip compute circuits configured to receive the pixel data via the interconnects and process the pixel data, the on-chip compute circuits comprising: a machine learning (ML) model accelerator configured to implement a convolutional neural network (CNN) model to process the pixel data; a first memory to store coefficients of the CNN model and instruction codes; a second memory to store the pixel data of a frame; and a controller configured to execute the codes to control operations of the ML model accelerator, the first memory, and the second memory.

This patent provides a method and apparatus for acquiring imagery with improve spatial resolution through an apparatus called a “light painting imaging device”. Other aspects of this invention correct for barrel distortion and pincushion distortion.

[Object] Provided is an electronic apparatus capable of Preventing image Quality deterioration of an image captured by a camera while reducing a bezel width.

[Solving Means] An electronic apparatus according to the present disclosure includes a display unit disposed on a first surface, a first imaging unit disposed on the side opposite to a display surface of the display unit, and a second imaging unit disposed on a second surface on the side opposite to the first surface. Sensitivity of the first imaging unit to a first wavelength band that includes blue light is higher than sensitivity of the second imaging unit to the first wavelength band. In addition, a ratio of blue light detection pixels in a pixel array of the first imaging unit may be higher than a ratio of blue light detection pixels in a pixel array of the second imaging unit.

A sensor device according to the present disclosure includes: a Peltier element; a sensor element thermally connected to a cooling surface of the Peltier element; and a package substrate that is thermally connected to a heat dissipation surface of the Peltier element and accommodates the Peltier element and the sensor element. In addition, the package substrate has a heat dissipation member, made of a material having a higher thermal conductivity than a material of the package substrate, on at least a part of a surface facing the heat dissipation surface of the Peltier element.

Provided is a semiconductor element capable of inspecting a plurality of wires formed in parallel. A semiconductor element according to an embodiment includes: a first circuit (45B) connected to a first position of each of a plurality of wires of a first wire group (31) including the plurality of wires; a second circuit (45A) connected to a second position corresponding to an end of each of the plurality of wires; and a plurality of connection units (43) that connects a third circuit (14) with each of the plurality of wires, the plurality of connection units (43) being provided on a one-to-one basis to the plurality of wires between the first position and the second position of each of the plurality of wires.

Solid-state imaging elements are disclosed. In one example, an upstream circuit block generates a predetermined reset level and a plurality of signal levels each corresponding to an exposure amount, and causes capacitive elements, different from each other, to hold them. A selection circuit sequentially performs control to connect the capacitive element in which the reset level is held to a predetermined downstream node, control to disconnect capacitive elements from the downstream node, and control to connect the capacitive element in which any of the plurality of signal levels is held to the downstream node. A downstream reset transistor initializes a level of the downstream node when the capacitive elements are disconnected from the downstream node. A downstream circuit sequentially reads the reset level and the plurality of signal levels via the downstream node

An imaging system has a imaging array on a semiconductor chip which also includes circuit the elements NPU and SRAM to rapidly identify target objects in the imaging data and output their high level representations with low power consumption.