A passive device packaging structure embedded in a glass medium according to an embodiment of the present disclosures includes a glass substrate and at least one capacitor embedded in the glass substrate. The capacitor includes an upper electrode, a dielectric layer, and a lower electrode. The glass substrate is provided on its upper surface with a cavity, the dielectric layer covers a surface of the cavity and has an area larger than that of the cavity. The upper electrode is provided on the dielectric layer. The dielectric layer and the lower electrode are connected by a metal via pillar passing through the glass substrate.

A wafer-level manufacturing method for embedding a passive element in a glass substrate is disclosed. A highly doped silicon wafer is dry etched to form a highly doped silicon mould wafer, containing highly doped silicon passive component structures mould seated in cavity arrays; a glass wafer is anodically bonded to the highly doped silicon mould wafer in vacuum pressure to seal the cavity arrays; the bonded wafers are heated so that the glass melts and fills gaps in the cavity arrays, annealing and cooling are performed, and a reflowed wafer is formed; the upper glass substrate of the reflowed wafer is grinded and polished to expose the highly doped silicon passives; the passive component structure mould embedded in the glass substrate is fully etched; the blind holes formed in the glass substrates after the passive component structure mould has been etched is filled with copper by electroplating; the highly doped silicon substrate and unetched silicon between the cavity arrays are etched, and several glass substrates embedded with a passive element are obtained; to form electrodes for the passives, a metal adhesion layer is deposited, and a metal conductive layer is electroplated. The process is simple, costs are low, and the prepared passive elements have superior performance.

Polymer-ceramic composites, in particular for the field of electronics, include grains of titanium suboxides of general formulation TiO.sub.x in which x is between 1.00 and 1.99, limits included, and/or of barium and/or strontium titanate suboxides of general formulation Ba.sub.(1-m)Sr.sub.mTiO.sub.y in which y is between 1.50 and 2.99, limits included, and m is between 0 and 1, limits included.

A touch substrate manufactured by three-dimensional printing and a method for manufacturing the same are disclosed. The method for manufacturing the touch substrate works together with a three-dimensional printer. The three-dimensional printer includes a first nozzle, a second nozzle, and a light source. The method includes the steps of: jetting a photocuring material by the first nozzle and exposing the photocuring material to the light source to form a base layer; jetting a conductive material on the base layer by the second nozzle and exposing the conductive material to the light source to form a touch electrode layer; and jetting the photocuring material on the base layer and the touch electrode layer by the first nozzle and exposing the photocuring material to the light source to form a protective layer. The touch electrode layer is embedded between the base layer and the protective layer.

A method for producing a printed circuit board (13, 15, 16) with multilayer subareas in sections, characterized by the following steps: a) providing at least one conducting foil (1, 1′) and application of a dielectric insulating foil (3, 3′) to at least one subarea of the conducting foil; b) applying a structure of conducting paths (4, 4′) to the insulating layer (3, 3′); c) providing one further printed circuit board structure; d) joining of the further printed circuit board structure with the conducting foil (1, 1′) plus insulating layer (3, 3′) and conducting paths (4, 4′) by interposing a prepreg layer (5, 85; 18, 18′), and e) laminating the parts joined in step d) under pressing pressure and heat; and a printed circuit board produced according to this method.

A semiconductor package includes a metal baseplate having a die attach region and a peripheral region, a transistor die having a reference terminal attached to the die attach region and an RF terminal facing away from the baseplate, and a multilayer circuit board having a first side attached to the peripheral region and a second side facing away from the baseplate. The multilayer circuit board includes two embedded electrically conductive layers that are separated from the first and second sides by layers of composite fiber, and an embedded dielectric layer disposed between the two embedded electrically conductive layers. The embedded dielectric layer has a higher dielectric constant than the layers of composite fiber.

A plurality of electrically conductive material layers and a plurality of dielectric layers are alternately stacked on a second substrate. The plurality of electrically conductive material layers comprise first and second patterns. The first pattern comprises at least a first pair of overlaying areas free of the electrically conductive material, and the second pattern comprises at least a second pair of overlaying areas free of the electrically conductive material. The first pair of areas overlay areas of the second pattern having the electrically conductive material and the second pair of areas overlay areas of the first pattern having the electrically conductive material. The plurality of electrically conductive material layers are electrically isolated from one another by the dielectric layers.

An electronic component is described which includes a first transistor encased in a first package, the first transistor being mounted over a first conductive portion of the first package, and a second transistor encased in a second package, the second transistor being mounted over a second conductive portion of the second package. The component further includes a substrate comprising an insulating layer between a first metal layer and a second metal layer. The first package is on one side of the substrate with the first conductive portion being electrically connected to the first metal layer, and the second package is on another side of the substrate with the second conductive portion being electrically connected to the second metal layer. The first package is opposite the second package, with at least 50% of a first area of the first conductive portion being opposite a second area of the second conductive portion.

A film stack made from compacted green films and capable of being sintered to form a ceramic component with monolithic multi-layer structure is disclosed. The film stack includes a functional layer comprising a green film comprising a functional ceramic and a tension layer comprising a green film comprising a dielectric material. The tension layer is directly adjacent to the functional layer in the multi-layer structure. The multilayer structure also includes a first metallization plane and second metallization plane. The functional layer is between the first metallization plane and the second metallization plane.

A capacitive touch device is described. The device comprises a substrate and a plurality of co-planar capacitive touch switches and conductive tracks connected to the capacitive touch switches disposed directly on a face of the substrate. The capacitive touch switches include first and second capacitive touch switches which are adjacent, separated by a channel and which are electrically isolated from each other. The capacitive touch switches include third and fourth capacitive touch switches which are electrically isolated from the first and second capacitive touch switches, but which are electrically connected to each other by a conductive track which runs through the channel.