A semiconductor composite device is provided that includes a voltage regulator, a package board, and a load, and converts an input DC voltage into a different DC voltage to supply the converted DC voltage to the load. The VR includes a semiconductor active element. The package board includes a C layer in which a capacitor is formed, and an L layer in which an inductor is formed. A plurality of through holes penetrate the C layer and the L layer in a direction perpendicular to the mounting face in the package board. The capacitor is connected to the load through the through hole. The inductor is connected to the load through the through hole and to the VR through the through hole.

A module substrate antenna includes: a laminate in which a plurality of ferrite layers are stacked; antennal coils provided on surfaces of the respective ferrite layers; a connection pad connected to an external circuit; and a lead wire provided between the laminate and the connection pad. In the laminate, the antenna coils are two types of the antenna coils, and the two types of the antenna coils are alternately stacked.

A processor substrate includes: an electrically insulating material having a first main side and a second main side opposite the first main side; a plurality of electrically conductive structures embedded in the electrically insulating material and configured to provide an electrical interface at the first main side of the electrically insulating material and to provide electrical connections from the electrical interface to the second main side of the electrically insulating material; and a power device module embedded in the electrically insulating material and configured to convert a voltage provided at the second main side of the electrically insulating material and which exceeds a voltage limit of the processor substrate to a voltage that is below the voltage limit of the processor substrate. An electronic system that includes the processor substrate is also described.

A printed circuit board (PCB) comprises a blind via and a discrete component vertically embedded within the blind via.

Apparatus and methods of automatically trimming a PCB-based LC circuit. The apparatus may comprise an interface to a printed circuit board (PCB). The PCB may include a PCB inductor and a PCB capacitor to form an LC circuit. The LC circuit may have an LC circuit frequency. The apparatus may comprise a variable capacitor communicatively coupled to the interface and configured to adjust an effective capacitance of the LC circuit.

A capacitor bank structure includes a plurality of capacitors, a protection material, a first dielectric layer and a plurality of first pillars. The capacitors are disposed side by side. Each of the capacitors has a first surface and a second surface opposite to the first surface, and includes a plurality of first electrodes and a plurality of second electrodes. The first electrodes are disposed adjacent to the first surface for external connection, and the second electrodes are disposed adjacent to the second surface for external connection. The protection material covers the capacitors, sidewalls of the first electrodes and sidewalls of the second electrodes, and has a first surface corresponding to the first surface of the capacitor and a second surface corresponding to the second surface of the capacitor. The first dielectric layer is disposed on the first surface of the protection material, and defines a plurality of openings to expose the first electrodes. The first pillars are disposed in the openings of the first dielectric layer and protrude from the first dielectric layer.

An element assembly has a structure in which insulator layers including first and second insulator layers are laminated in an up-down direction. The first insulator layer is above the second insulator layer. A radiant conductor layer is on an upper surface of the first insulator layer. A first capacitance defining portion includes a first interlayer connection conductor passing through one or more of the insulator layers in the up-down direction. The first interlayer connection conductor is electrically connected to the radiant conductor layer. The radiant conductor layer, a ground conductor, and the first capacitance defining portion define and function as a patch antenna. When the first interlayer connection conductor is electrically connected to the radiant conductor layer, a distance from a lower end of the first interlayer connection conductor to the ground conductor in the up-down direction is shorter than a distance from the radiant conductor layer to the ground conductor in the up-down direction.

A multilayer substrate includes a stacked body including a first main surface, and a conductor pattern (including a mounting electrode provided on the first main surface, and a first auxiliary pattern provided on the first main surface). The stacked body includes a plurality of insulating base material layers made of a resin as a main material and stacked on one another. The first auxiliary pattern is located adjacent to or in a vicinity of the mounting electrode. The mounting electrode, in a plan view of the first main surface (when viewed in the Z-axis direction), is interposed between a different conductor pattern (the mounting electrode) and the first auxiliary pattern.

Embodiments disclosed herein include package substrates and methods of forming such package substrates. In an embodiment a package substrate comprises a glass core, and a vertically oriented inductor embedded in the glass core. In an embodiment, the inductor comprises vertical vias through the glass core, and where the vertical vias are electrically coupled together by conductive traces over a surface of the glass core to provide a plurality of conductive turns.

Devices, systems, and methods for serial communication over a galvanically isolated channel are disclosed. A device includes a first IC device interface, first TO components connected to the first IC device interface, a second IC device interface, second IO components connected to the second IC device interface, an insulator layer having a first major surface and a second major surface, at least one pair of capacitor plates and corresponding interconnection paths on the first major surface, and at least one pair of capacitor plates and corresponding interconnection paths on the second major surface, wherein the at least one pair of capacitor plates on the first major surface of the insulator layer are aligned with the at least one pair of capacitor plates on the second major surface of the insulator layer to form at least one pair of capacitors.