A component package includes a printed circuit board; a first electronic component disposed in a first region on the printed circuit board; a second electronic component disposed in a second region on the printed circuit board; and a metal wall disposed on the printed circuit board and spatially partitioning the first region and the second region on a plane. The metal wall is directly connected to the printed circuit board.

A component carrier includes a stack with at least one electrically conductive layer structure, at least one electrically insulating layer structure, and a hole in the stack having a first hole portion covered with metal and having a second hole portion not covered with metal, wherein the second hole portion is defined by an anti-plating dielectric structure and an electroless plateable separation barrier.

A wiring board (10) includes a substrate (11) and a mesh wiring layer (20) disposed on the substrate (11) and including a plurality of wiring lines (21, 22). The substrate (11) has a transmittance of 85% or more for light with a wavelength of 400 nm or more and 700 nm or less. The wiring lines (21, 22) have a surface roughness Ra, and the surface roughness Ra is 100 nm or less.

A method for manufacturing a wiring substrate includes preparing a substrate including an insulating layer and metal foils, forming a through hole in the substrate to penetrate through the insulating layer and foils, forming a first plating film on the substrate such that the first film is formed on the entire surface of each metal foil and the inner wall of the hole, laminating one or more resin sheets on the first film such that the resin sheet or sheets cover the first film on the entire surface of a respective one of the foils, pressing the resin sheet or sheets such that resin is extruded from the resin sheet or sheets into the hole and fills space surrounded by the first film inside the hole, removing the resin sheet or sheets, and forming a second plating film on the substrate to cover surface of the resin in the hole.

A method for manufacturing a wiring board is capable of forming a metal layer included in a wiring layer to have an even thickness. The method includes preparing a conductive first underlayer on a surface of a substrate; a conductive second underlayer on a surface of the first underlayer; and a seed layer on a surface of the second underlayer and containing metal. The method disposes a solid electrolyte membrane between an anode and the seed layer as a cathode; applies voltage between the anode and the first underlayer to form a metal layer on the surface of the seed layer; removes an exposed portion of the second underlayer without the seed layer from the substrate; and removes an exposed portion of the first underlayer without the seed layer from the substrate. The first underlayer is a material having a higher electrical conductivity than that of the second underlayer.

A flexible circuit board and a manufacturing method thereof are provided. The flexible circuit board includes a circuit structure, a first cover layer, and a second cover layer. The circuit structure has a top surface and a bottom surface opposite to the top surface. The circuit structure includes multiple circuit layers and multiple insulating layers stacked alternately. A material of the insulating layers is a photosensitive dielectric material and a Young's modulus of the insulating layers is between 0.36 GPa and 8 GPa. The first cover layer is disposed on the top surface of the circuit structure. The second cover layer is disposed on the bottom surface of the circuit structure.

A printed wiring board includes a first resin insulating layer, a conductor layer on the first resin insulating layer, and a second resin insulating layer formed on the first resin insulating layer such that the second resin insulating layer is covering the conductor layer. The conductor layer includes a first circuit having a width of 15 μm or less and a rectangular cross-sectional shape, a second circuit having a trapezoidal cross-sectional shape, a third circuit, a fourth circuit, a fifth circuit, and a sixth circuit, a space between the first and third circuits has a width of 14 μm or less, a space between the first and fourth circuits has a width of 14 μm or less, a space between the second and fifth circuits has a width of 20 μm or more, and a space between the second and sixth circuits has a width of 20 μm or more.

A resist layer forming method includes a process of laminating a resist layer on a base at a first pressure using a laminate roller having a first temperature, and a process of pressing the resist layer against the base at a second pressure higher than the first pressure using a metal plate having a second temperature lower than the first temperature.

The wiring board according to the present disclosure includes: a first insulating layer including insulating particles; a plurality of first conductors located on the first insulating layer at an interval of a first distance from each other; a second conductor located on the first insulating layer at an interval of a second distance from the first conductor; and a second insulating layer located on the first insulating layer to cover the first conductor and the second conductors and including the insulating particles. When a boundary portion between the first insulating layer and the second insulating layer is viewed in cross-section in the thickness direction, the ratio of a first area occupied by the insulating particles in a first boundary portion including the first distance is higher than the ratio of a second area occupied by the insulating particles in a second boundary portion including the second distance.

The present disclosure provides a wiring structure, a preparation method thereof, and a display device. The wiring structure includes a substrate; a pre-arranged layer located on the substrate; and an electrode wiring covering the pre-arranged layer; wherein in the direction perpendicular to an extending direction of the electrode wiring and parallel to a plane on which the substrate is located, an orthographic projection of the pre-arranged layer on the substrate is located within an orthographic projection of the electrode wiring on the substrate, and a side surface of the pre-arranged layer is inclined relative to the plane on which the substrate is located.