A wiring substrate includes an insulating layer including inorganic fillers and resin, and a conductor layer formed on a surface of the insulating layer and having a conductor pattern. The surface of the insulating layer has an arithmetic average roughness Ra in the range of 0.05 μm to 0.5 μm, the conductor layer includes a metal film formed on the surface of the insulating layer, and the inorganic fillers include a first inorganic filler including particles such that each of the particles has a portion of a surface separated from the resin and forming a gap with respect to the resin of the insulating layer and that the metal film of the conductor layer includes part formed in the gap between the first inorganic filler and the resin.

A wiring board includes an insulating layer; an insulating oxide film that is formed by forming a film of metal oxide or semimetal oxide on a surface of the insulating layer; a seed layer that is made of metal and that is stacked on the insulating oxide film; and an electrode that is made of metal and that is formed on the seed layer, wherein the insulating oxide film and the seed layer are removed from an area not overlapping the electrode to expose the insulating layer.

An insulating sheet for use in forming an insulating layer of an interconnect substrate includes a semi-cured insulating resin layer, a semi-cured protective resin layer laminated on an upper surface of the insulating resin layer, and a cover layer laminated on an upper surface of the protective resin layer, wherein the protective resin layer has lower resistance to a predetermined solution than the insulating resin layer has, the predetermined solution being capable of dissolving the insulating resin layer and/or the protective resin layer.

A method for manufacturing a printed wiring board includes forming the outermost conductor layer on the outermost resin insulating layer, forming a solder resist layer on the outermost resin insulating layer such that the solder resist layer covers the outermost conductor layer formed on the outermost resin insulating layer, irradiating plasma upon an exposed surface of the solder resist layer formed on the outermost conductor layer, forming a catalyst on the exposed surface of the solder resist layer formed on the outermost conductor layer, and forming an electroless plating layer on the exposed surface of the solder resist layer via the catalyst formed on the exposed surface of the solder resist layer such that the electroless plating layer has a film thickness in a range of 0.22 μm to 0.38 μm.

A wiring board (10) includes a substrate (11) that is transparent and a wiring pattern region (20) that is disposed on the substrate (11) and that includes a plurality of wiring lines (21, 22). The wiring pattern region (20) has a sheet resistance of less than or equal to 5 Ω/sq, and each wiring line (21, 22) has a maximum width of less than or equal to 3 μm when viewed at a viewing angle of 120°.

A lamination circuit board structure lamination circuit board structure includes a printed circuit board substrate including conductive wiring traces on at least a first wiring face, a prepreg layer formed over the first wiring face, and a patch having an area smaller than 1,000 mm.sup.2. The patch includes conductive wiring traces formed on a wiring face and is laminated to the printed circuit board substrate over the prepreg layer, oriented with the wiring face in contact with and pressed into the prepreg layer. Portions of the prepreg layer fill interstices between the conductive wiring traces.

A laminate for printed wiring board is used in a method of manufacturing printed wiring boards that includes a process of forming a circuit by any one of a semi-additive method, a partly additive method, a modified semi-additive method, and an embedding method. The laminate includes an insulating resin substrate, a metal layer 1 and a metal layer 2 in this order. When a cross section that is parallel to the thickness direction of the laminate is processed by means of ion milling and the cross sections of the metal layer 1 and the metal layer 2 were observed with EBSD, each of the metal layer 1 and the metal layer 2 has one or plural crystal grain(s) at the processed cross section, and an area ratio of the total area of crystal grains of which a difference in angle of the <100> crystal direction from a perpendicular of the processed cross section is 15° or less from among the one or plural crystal grains to the total area of the plural crystal grains was 15% or higher but less than 97% in the metal layer 1 and the metal layer 2.

A copper heat dissipation material having a satisfactory heat dissipation performance is provided. The copper heat dissipation material has an alloy layer containing at least one metal selected from Cu, Co, Ni, W, P, Zn, Cr, Fe, Sn and Mo on one or both surfaces, in which surface roughness Sz of the one or both surfaces, measured by a laser microscope using laser light of 405 nm in wavelength, is 5 μm or more.

The disclosure relates to a method for manufacturing a transfer film including an electrode layer, the method comprising: an electrode layer formation step of forming an electrode layer on a carrier member by using a conductive material; a placement step of placing the carrier member on at least one side of an insulating resin layer respectively; a bonding step of bonding the carrier member and the insulating resin layer together by applying pressure thereto; and a transfer step of removing the carrier member to transfer the electrode layer on the insulating resin layer.

First, a patterned substrate including an insulating substrate, a conductive seed layer, and an insulating layer is prepared. The seed layer is disposed on the insulating substrate, and consists of a first part having a predetermined pattern corresponding to the wiring pattern and a second part as a part other than the first part. The insulating layer is disposed on the second part of the seed layer. Subsequently, a metal layer having a thickness larger than a thickness of the insulating layer is formed on the first part of the seed layer. Here, a voltage is applied between an anode and the seed layer while a resin film containing a metal ion-containing solution is disposed between the patterned substrate and the anode and the resin film and the seed layer are brought into pressure contact. Subsequently, the insulating layer and the second part of the seed layer are removed.