A mounting device for mounting electronic components, wherein the mounting device comprises an electrically conductive structure having a first value of thermal expansion in at least one pre-defined spatial direction, an electrically insulating structure having a second value of thermal expansion in the at least one pre-defined spatial direction being different from the first value and being arranged on the electrically conductive structure, and a thermal expansion adjustment structure having a third value of thermal expansion in the at least one pre-defined spatial direction, wherein the third value is selected and the thermal expansion adjustment structure is located so that thermally induced warpage of the mounting device resulting from a difference between the first value and the second value is at least partially compensated by the thermal expansion adjustment structure.

A method of forming a high-conductivity electrical interconnect on a substrate may include forming a graphene film with a plurality of graphene members, depositing a metal over the graphene film, and providing a metallic overlay that connects the plurality of graphene members together through the depositing operation to form a covered graphene film.

The present disclosure relates to a transparent substrate including: a resin pattern layer including a plurality of grooves respectively including side surfaces and a bottom surface; and, a conductive layer formed within the grooves, wherein a line width of the conductive layer is 0.1 μm to 3 μm and an average height of the conductive layer is 5% to 50% of a maximum depth of each of the grooves, and a manufacturing method thereof, such that simplicity in a manufacturing process and a consecutive process are enabled, manufacturing costs are inexpensive, and a transparent substrate having superior electrical conductivity and transparency characteristics is manufactured.

Techniques for forming highly stretchable electronic interconnect devices are disclosed herein. In one embodiment, a method of fabricating an electronic interconnect device includes forming a layer of an adhesion material onto a surface of a substrate material capable of elastic and/or plastic deformation. The formed layer of the adhesion material has a plurality of adhesion material portions separated from one another on the surface of the substrate material. The method also includes depositing a layer of an interconnect material onto the formed layer of the adhesion material. The deposited interconnect material has regions that are not bonded or loosely bonded to corresponding regions of the substrate material, such that the interconnect material may be deformed more than the adhesion material attached to the substrate material. In certain embodiments, the interconnect material can also include a plurality of wrinkles on a surface facing away from the substrate material.

Techniques for forming highly stretchable electronic interconnect devices are disclosed herein. In one embodiment, a method of fabricating an electronic interconnect device includes forming a layer of an adhesion material onto a surface of a substrate material capable of elastic and/or plastic deformation. The formed layer of the adhesion material has a plurality of adhesion material portions separated from one another on the surface of the substrate material. The method also includes depositing a layer of an interconnect material onto the formed layer of the adhesion material. The deposited interconnect material has regions that are not bonded or loosely bonded to corresponding regions of the substrate material, such that the interconnect material may be deformed more than the adhesion material attached to the substrate material. In certain embodiments, the interconnect material can also include a plurality of wrinkles on a surface facing away from the substrate material.

A temperature measuring device, a process for manufacturing the device, and a system for measuring an impact point incorporating the device. According to one aspect, a temperature measuring device includes a thin film sheet made of magneto-metallic material such that, in use and the presence of an applied magnetic field, a change of temperature in one region of the sheet generates an electric voltage in the region, the generated electric voltage being readable through means for reading electric voltage corresponding to the region. According to another aspect, there is a process for manufacturing the device. According to yet another aspect, there is a system for measuring an impact point, of radiation or particles, incorporating the device.

A conductor includes a substrate, a first conductive layer disposed on the substrate and including two or more islands including graphene, and a second conductive layer disposed on the first conductive layer and including a conductive metal nanowire, wherein at least one of an upper surface and a lower surface of the islands including graphene includes a P-type dopant.

Methods for forming electrical circuitries on three-dimensional (3D) structures and devices made using the methods. A method includes additively forming and photocuring a 3D structure. The 3D structure is characterized by one or more three-dimensional flexible interconnects (3FIs), an upper level, a lower level, and a pedestal portion. The pedestal portion includes an undercut. The undercut defines an upper level overhang configured to define a mask region over a portion of the lower level. The method includes forming at least two electrically isolated planes of electronic circuitry by directionally depositing a selected material on the one or more 3FIs, the upper level, and one or more non-masked portions of the lower level.

Methods for forming electrical circuitries on three-dimensional (3D) structures and devices made using the methods. A method includes additively forming and photocuring a 3D structure. The 3D structure is characterized by one or more three-dimensional flexible interconnects (3FIs), an upper level, a lower level, and a pedestal portion. The pedestal portion includes an undercut. The undercut defines an upper level overhang configured to define a mask region over a portion of the lower level. The method includes forming at least two electrically isolated planes of electronic circuitry by directionally depositing a selected material on the one or more 3FIs, the upper level, and one or more non-masked portions of the lower level.

An integrated circuit (IC) die package substrate comprises a first trace upon, or embedded within, a dielectric material. The first trace comprises a first metal and a first via coupled to the first trace. The first via comprises the first metal and a second trace upon, or embedded within, the dielectric material. A second via is coupled to the second trace, and at least one of the second trace or the second via comprises a second metal with a different microstructure or composition than the first metal.