An electronic device is provided, the electronic device includes a driving substrate, the driving substrate includes a plurality of first grooves and a plurality of second grooves, the first grooves and the second grooves have different sizes, at least one first electronic component of the plurality of first electronic components is disposed in one of the plurality of first grooves, at least one second electronic component of the plurality of second electronic components is disposed in one of the plurality of second grooves, a maximum length passing through a center of a bottom surface of the at least one first electronic component is defined as L1, a bottom length of one side of at least one second groove among the second grooves is defined as L2, and the at least one first electronic component and the at least one second groove satisfy the condition of L1>L2.

Disclosed embodiments include alignment apparatuses for circuit boards, inverter assemblies, and methods for fabricating an assembly with a circuit board placed on an alignment apparatus. An illustrative apparatus includes an electrically insulative substrate having a first substantially planar surface and a second substantially planar surface forming an opposing side of the first substantially planar surface. The second substantially planar surface defines therein self-aligning features that are configured to align at least one power module pin with the electrically insulative substrate. The first substantially planar surface has at least one alignment feature configured to align a printed circuit board with the electrically insulative substrate. The apparatus also includes a routing feature coupled to the electrically insulative substrate. The routing feature is configured to route at least one low voltage conductor.

A semiconductor assembly includes a semiconductor package that includes first and second transistor dies embedded within a package body, the first and second transistor dies being arranged laterally side by side within the package body such that a first load terminal of the first transistor die faces an upper surface of the package body and such that a second load terminal of the second transistor die faces the upper surface of the package body, and a discrete capacitor mounted on the semiconductor package such that a first terminal of the discrete capacitor is directly over and electrically connected to the first load terminal of the first semiconductor die and such that a second terminal of the discrete capacitor is directly over and electrically connected with the second load terminal of the second semiconductor die.

A stackable via package includes a substrate having an upper surface and a trace on the upper surface, the trace including a terminal. A solder ball is on the terminal. The solder ball has a solder ball diameter A and a solder ball height D. A via aperture is formed in a package body enclosing the solder ball to expose the solder ball. The via aperture includes a via bottom having a via bottom diameter B and a via bottom height C from the upper surface of the substrate, where A<B and 0=<C<1/2×D. The shape of the via aperture prevents solder deformation of the solder column formed from the solder ball as well as prevents solder bridging between adjacent solder columns.

According to an embodiment disclosed in the specification, an electronic device comprises a battery disposed inside the electronic device; a printed circuit board (PCB) disposed inside the electronic device; at least one electronic component disposed on the PCB; and a first buck converter having a first end and a second end, wherein the first end is routed to the battery; and a second buck converter having a first end and a second end, wherein the first end is selectively electrically connected to the second end of the first buck converter, and the second end is routed to the at least one electronic component, and wherein the first buck converter and the second buck converter are configured to boost a voltage provided from the battery through an electrical path formed from the battery by the first end of the first buck converter, and the second end of the first buck converter, the first end of the second buck converter and the second end of the second buck converter to the at least one electronic component.

A device source wafer includes a wafer substrate, devices formed on or in the wafer substrate at a location on the wafer substrate, and test structures disposed on the wafer substrate connected to some but not all of the devices. The devices include a first device disposed at a first location and a second device disposed at a second different location on the wafer substrate. The test structures include at least a first test structure connected to the first device and a second test structure connected to the second device. The first test structure is adapted to measuring a characteristic of the first device and the second test structure is adapted to measuring the characteristic of the second device. An estimated characteristic of unmeasured devices is derived from the first and second device locations and measured characteristics and the device is selected based on the estimated characteristic.

Provided is an electronic component including a pad region including a plurality of pads extending along corresponding extension lines and arranged in a first direction, and a signal wire configured to receive a driving signal from the pad region, wherein the plurality of pads include a plurality of first pads arranged continuously and a plurality of second pads arranged continuously, and extension lines of the plurality of first pads substantially converge into a first point and extension lines of the plurality of second pads substantially converge into a second point different from the first point.

One feature pertains to a modular design of a motherboard for a computer system. The mother board is disaggregated into a CPU board and an IO board. The CPU board contains at least one CPU, the associated memory subsystem and the voltage regulator module. The integrated IO ports escape to a high speed connector mating with its counterpart on an IO board which contains all peripheral devices including system logic not part of the CPU. In a multi-socket configuration the CPUs are on the CPU board and the processor interconnects are routed directly in a point to point manner.

A PCB bridge for interconnection of two or more semiconductor chips for data communication between the semiconductor chips includes a plurality of metal strips; and a dielectric material disposed in between the plurality of metal strips. The PCB bridge is employed in a vertical direction in a semiconductor module for interconnection of two or more semiconductor chips, the vertical direction of the PCB bridge provides a flexible impedance matching by adjusting the dielectric material and a trace width of the PCB bridge, and the vertical direction of the PCB bridge avoids signal reflections by matching the impedance to a source, and a trace length of the PCB bridge is limited by spacing in between two semiconductor chips which further limited inductance of the trace of the PCB bridge.

A power module for the controllable electrical power supply of a consumer includes a plurality of housed power semiconductors each with an electrically non-insulated heat discharge surface, a printed circuit board, a heat sink, one or more insulation plates, wherein the printed circuit board is arranged on a side of the power semiconductor in an orthogonal direction opposite the heat sink, wherein the insulation plate is arranged between the housed power semiconductors and a cooling surface of the heat sink, wherein one insulation plate in each case is interlockingly connected by one side to one electrically non-insulated heat discharge surface of a housed power semiconductor and is interlockingly connected by the other side to the heat sink.