Patent classifications
H05K3/386
Flexible membrane for applying a pattern to a substrate
A method is disclosed for applying an electrical conductor to a solar cell, which comprises providing a flexible membrane with a pattern of groove formed on a first surface thereof, and loading the grooves with a composition comprising conductive particles. The composition is, or may be made, electrically conductive. Once the membrane is loaded, the grooved first surface of the membrane is brought into contact with a front or/and back of a solar cell. A pressure is then applied between the solar cell and the membrane(s) so that the composition loaded to the grooves adheres to the solar cell. The membrane(s) and the solar cell are separated and the composition in the groove is left on the solar cell surface. The electrically conductive particles in the composition are then sintered or otherwise fused to form a pattern of electrical conductor on the solar cell, the pattern corresponding to the pattern formed in the membrane(s).
Increasing adhesion of metal-organic interfaces by silane vapor treatment
A method of improving the adhesion of a metal-organic interface in an electronic device includes providing a substrate with a metal structure, depositing a mono-layer of a selected silane composition on a surface of the metal structure with a vapor of the selected silane composition, and coating the treated surface with an organic material.
Laminated film, light-emitting device using the same, and method for manufacturing light-emitting device
A laminated film in which a heat-resistant base film and a metal foil are bonded using an adhesive is provided with a barrier layer that prevents chemicals from entering the adhesive layer, between the metal foil and the adhesive layer. The barrier layer is made of a heat-resistant resin similar to that of the base film and has a water absorption rate of 1% or less. The adhesive layer is a silicone-based resin and has a thickness of 40 μm or more after drying.
Application of electrical conductors to an electrically insulating substrate
A method is disclosed for applying an electrical conductor to an electrically insulating substrate, which comprises providing a flexible membrane with a pattern of groove formed on a first surface thereof, and loading the grooves with a composition comprising conductive particles. The composition is, or may be made, electrically conductive. Once the membrane is loaded, the grooved first surface of the membrane is brought into contact with a front or/and back of the substrate. A pressure is then applied between the substrate and the membrane(s) so that the composition loaded to the grooves adheres to the substrate. The membrane(s) and the substrate are separated and the composition in the groove is left on the surface of the electrically insulating substrate. The electrically conductive particles in the composition are then sintered to form a pattern of electrical conductors on the substrate, the pattern corresponding to the pattern formed in the membrane(s).
Apparatus and method for encapsulating an electronic component
An apparatus for encapsulating at least one electronic component disposed on a printed circuit board may include a liquid-tight enclosure that surrounds the electronic component and that is fixed with respect to the electronic component and the circuit board, and an encapsulating material disposed inside the enclosure and encapsulating the electronic component. The enclosure may include at least one sidewall and a top. The at least one sidewall may include a rigid material, a lower edge that is proximal to the printed circuit board, an upper edge that is distal from the circuit board, and a height above the circuit board that is no more than 0.003 inches greater than a height of the electronic component above the circuit board. The top may include a solid surface disposed on the upper edge of the at least one sidewall, where the at least one sidewall and the top form the enclosure.
Dielectric substrate and method of forming the same
The present disclosure relates to a dielectric substrate that may include a polymer based core film, and a fluoropolymer based adhesive layer. The polymer based core film may include a resin matrix component, and a ceramic filler component. The ceramic filler component may include a first filler material. The particle size distribution of the first filler material may have a D.sub.10 of at least about 1.0 microns and not greater than about 1.7, a D.sub.50 of at least about 1.0 microns and not greater than about 3.5 microns, and a D.sub.90 of at least about 2.7 microns and not greater than about 6 microns.
Interfacial layer for high resolution lithography (HRL) and high speed input/output (IO or I/O) architectures
Embodiments described herein are directed to interfacial layers and techniques of forming such interfacial layers. An interfacial layer having one or more light absorbing molecules is on a metal layer. The light absorbing molecule(s) may comprise a moiety exhibiting light absorbing properties. The interfacial layer can assist with improving adhesion of a resist layer to the metal layer and with improving use of one or more lithography techniques to fabricate interconnects and/or features using the resist and metal layers for a package substrate, a semiconductor package, or a PCB. For one embodiment, the interfacial layer includes, but is not limited to, an organic interfacial layer. Examples of organic interfacial layers include, but are not limited to, self-assembled monolayers (SAMs), constructs and/or variations of SAMs, organic adhesion promotor moieties, and non-adhesion promoter moieties.
CIRCUIT BOARD
A circuit board according to an embodiment includes a first insulating portion including at least one insulating layer; a second insulating portion disposed on the first insulating portion and including at least one insulating layer; and a third insulating portion disposed under the first insulating portion and including at least one insulating layer; wherein the insulating layer constituting the first insulating portion includes a prepreg containing glass fibers, and wherein each of the insulating layers constituting the second and third insulating portions is made of resin coated copper (RCC).
Antenna module including printed circuit board and base station including the antenna module
The present disclosure relates to a communication method and system for converging a 5.sup.th-Generation (5G) communication system for supporting higher data rates beyond a 4.sup.th-Generation (4G) system with a technology for Internet of Things (IoT). The present disclosure may be applied to intelligent services based on the 5G communication technology and the IoT-related technology, such as smart home, smart building, smart city, smart car, connected car, health care, digital education, smart retail, security and safety services. An antenna module and a base station including the antenna module. The antenna module includes a printed circuit board in which at least one layer is stacked, a feeding unit disposed at one surface of the printed circuit board, and a first antenna spaced apart from the feeding unit by a predetermined first length.
CIRCUIT BOARD STRUCTURE AND MANUFACTURING METHOD THEREOF
A circuit board structure includes a first sub-board including a plurality of circuit patterns, a second sub-board including a plurality of pads, and a connecting structure layer having a plurality of through holes and including an insulating layer, first and second adhesive layers, and a plurality of conductive blocks. The first adhesive layer is directly connected to the first sub-board. The second adhesive layer is directly connected to the second sub-board. The through holes penetrate through the first adhesive layer, the insulating layer, and the second adhesive layer. The conductive blocks are located in the through holes. An upper surface and a lower surface of each conductive block are respectively lower than a first surface of the first adhesive layer and a second surface of the second adhesive layer relatively away from the insulating layer. Each circuit pattern contacts the upper surface, and each pad contacts the lower surface.